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STA321MPL1 数据表(PDF) 23 Page - STMicroelectronics |
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STA321MPL1 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 80 page  DocID029389 Rev 1 23/80 STA321MPL1 Registers 80 PDM and recombination IP interface 0x5C MRBist MHFail MHBad MHEnd MHAct MNFail MNBad MNEnd MNAct 0x5D RCTR1 Boost6db I²S_byp I²S_en mike_en mike_byp m_mode 0x5E PDMCT AdvM6 AdvM5 AdvM4 AdvM3 AdvM2 AdvM1 PDMSM[1:0] 0x5F RCTR2 bypRM1 CH1GG[5:0] 0x60 RCTR3 bypRM2 CH2GG[5:0] 0x61 RCTR4 bypRM3 CH3GG[5:0] 0x62 RCTR5 LP1en CH1NCA[5:0] 0x63 RCTR6 LP2en CH2NCA[5:0] 0x64 RCTR7 LP3en CH3NCA[5:0] 0x65 RCTR8 CH1TH_N[5:0] 0x66 RCTR9 CH2TH_N[5:0] 0x67 RCTR10 CH3TH_N[5:0] 0x68 RCTR11 CH1TH_H[5:0] 0x69 RCTR12 CH2TH_H[5:0] 0x6A RCTR13 CH3TH_H[5:0] Clock manager configuration/status registers 0x71 pllfrac1 PLFI15 PLFI14 PLFI13 PLFI12 PLFI11 PLFI10 PLFI9 PLFI8 0x72 pllfrac0 PLFI7 PLFI6 PLFI5 PLFI4 PLFI3 PLFI2 PLFI1 PLFI0 0x73 pll div PLLDD1 PLLDD0 PLLND5 PLLND4 PLLND3 PLLND2 PLLND1 PLLND0 0x74 pll conf0 PDPDC PLLFC PLSTRB PLSTBB PLIFD3 PLIFD2 PLIFD1 PLIFD0 0x75 pll conf1 PLLBYP PLLDPR LOWEN BST32K 0x76 pll stat PLLBYS PLLPDS OSCOK LOWCKS Biquad configuration 0x77 CBQ1 EBQ3_1 EBQ3_0 EBQ2_1 EBQ2_0 EBQ1_1 EBQ1_0 EBQ0_0 EBQ0_0 0x78 CBQ2 EBQ7_1 EBQ7_0 EBQ6_1 EBQ6_0 EBQ5_1 EBQ5_0 EBQ4_0 EBQ4_0 0x79 CBQ3 nshen EBQ9_1 EBQ9_0 EBQ8_0 EBQ8_0 RMS status registers 0x7A rmsZMH RZM15 RZM14 RZM13 RZM12 RZM11 RZM10 RZM9 RZM8 0X7B rmsZML RZM7 RZM6 RZM5 RZM4 RZM3 RZM2 RZM1 RZM0 0X7C rmsPOH RPO15 RPO14 RPO13 RPO12 RPO11 RPO10 RPO9 RPO8 0X7D rmsPOL RPO7 RPO6 RPO5 RPO4 RPO3 RPO2 RPO1 RPO0 Tristate startup/shutdown pop removal signals 0x80 DPT DPT4 DPT3 DPT2 DPT1 DPT0 0x81 CFR129 RL3 RL2 RL1 RL0 RD SID1 FBYP RTP 0x82 TSDLY1 UDDT15 UDDT14 UDDT13 UDDT12 UDDT11 UDDT10 UDDT9 UDDT8 0x83 TSDLY2 UDDT7 UDDT6 UDDT5 UDDT4 UDDT3 UDDT2 UDDT1 UDDT0 Table 9. Register summary (continued) Addr Name D7 D6 D5 D4 D3 D2 D1 D0 |
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