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STA321MPL1 数据表(PDF) 75 Page - STMicroelectronics |
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STA321MPL1 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 80 page  DocID029389 Rev 1 75/80 STA321MPL1 Startup/shutdown pop noise removal 80 7 Startup/shutdown pop noise removal 7.1 DPT: PWM and tristate delay (0x80) 7.2 Configuration register (0x81) D7 D6 D5 D4 D3 D2 D1 D0 DPT4 DPT3 DPT2 DPT1 DPT0 11 100 Bit RW RST Name Description 0RW 0 DPT0 Set a delay between the PWM and the tristate signal to compensate the external amplifier delay. 1RW 0 DPT1 2RW 1 DPT2 3RW 1 DPT3 4RW 1 DPT4 D7 D6 D5 D4 D3 D2 D1 D0 RL3 RL2 RL1 RL0 RD SID1 FBYP RTP 00 000 10 1 Bit RW RST Name Description 0RW 1 RTP Remove tristate initial pulses 1: remove the tristate initial pulses with frequency less than 16 kHz 0: the tristate initial pulses are not removed Bit RW RST Name Description 1 RW 0 FBYP Fault user-defined bypass mode 1: the fault internal management is disabled 0: the fault internal management is enabled Bit RW RST Name Description 2RW 1 SID1 Serial interface (I²S out) 1: SDO_56 is connected to the fault signal and SDO_78 outputs the tristate signal 0: I²S out normal |
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