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STA321MPL1 数据表(PDF) 47 Page - STMicroelectronics |
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STA321MPL1 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 80 page ![]() DocID029389 Rev 1 47/80 STA321MPL1 Registers 80 5.2.49 Channel 1 and 2 output timing (0x33) 5.2.50 Channel 3 and 4 output timing (0x34) 5.2.51 Channel 5 and 6 output timing (0x35) LnRT[3:0] Dynamic range compression (DRC) (db relative to volume + LnAT) 0000 - ∞ 0001 -38 dB 0010 -36 dB 0011 -33 dB 0100 -31 dB 0101 -30 dB 0110 -28 dB 0111 -26 dB 1000 -24 dB 1001 -22 dB 1010 -20 dB 1011 -18 dB 1100 -15 dB 1101 -12 dB 1110 -9 dB 1111 -6 dB D7 D6 D5 D4 D3 D2 D1 D0 C2OT2 C2OT1 C2OT0 C1OT2 C1OT1 C1OT0 10 0 0 00 D7 D6 D5 D4 D3 D2 D1 D0 C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0 11 0 0 10 D7 D6 D5 D4 D3 D2 D1 D0 C6OT2 C6OT1 C6OT0 C5OT2 C5OT1 C5OT0 10 1 0 01 |
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