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EPC635 数据表(PDF) 25 Page - Espros Photonics corp |
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EPC635 数据表(HTML) 25 Page - Espros Photonics corp |
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25 / 97 page  5.4.3. I2C bus timing SDA SCLK ACK MSB LSB Change of data allowed START condition STOP condition Data stable START condition Acknowledgment SDA SCL ACK MSB LSB t STA t SU t H t SCLL t SCLH t SDAF t SDAR t STO t STOSTA t SCLR t SCLF Figure 19: I2C bus timing top: Basic communication sequence below: Timing parameters Symbol Parameter Min. Max. Units fSCL I2C data rate 1 Mbit/s tSCLL SCL clock low time 0.5 µs tSCLH SCL clock high time 0.26 µs tSU SDA setup time 50 ns tH SDA hold time 0 ns tSDAR tSCLR SDA and SCL rise time 120 ns tSDAF tSCLF SDA and SCL fall time 120 ns tSTA Start condition hold time 0.26 µs tSTO Stop condition setup time 0.26 µs tSTOSTA Stop to start condition time (bus free) 0.5 µs Cb Capacitive load for each bus line 550 pF tSP Pulse width of the spikes that are suppressed by the analog filter 50 ns Table 12: I2C bus timing: Timing parameters (FM+) © 2017 ESPROS Photonics Corporation Characteristics subject to change without notice 25 / 97 Datasheet_epc635-V1.02 www.espros.com |
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