EPC635 datasheet(32/97 Pages) EPC

32 / 97 page

5.6.2. DLL filters

Two digital filter stages which average by counting the number of LED pulses (DLL_filter_control.dll_filter_ctrl_s1_sel) and DCS frames

(DLL_filter_control.dll_filter_ctrl_s2_sel), allow to adapt the DLL locking operation to slow changing environmental conditions, such as tem-

perature effects. The filter control loop re-applies averaged lock values only at those programmed count times back to DLL's delay line re -

gisters. DLL filter s1 allows binary count steps of 8, 16, 32, … 512 LED pulses; whereas DLL filter s2 uses 2, 4, 8, … 128 DCS frame

steps. Optimal s1 and s2 settings depend on the application system.

5.7. Pixel-field

5.7.1. Pixel coordinates

The epc635 pixel-field consists of a total of 168 x 72 pixels. 4 rows top/bottom and 6 columns left/right on the periphery of the pixel-field

contain dummy pixels. The active pixels for TOF and grayscale imaging modes are in the central rectangle area forming a full Half-QQVGA

resolution 160 x 60 pixel (Figure 29).

The upper-left corner (top view on chip) is the origin (4/6) of the epc635 pixel-field. X-axis starts at 4 and counts up to 163 to the right. Pixel

y-axis starts at 6 and counts up to 65 to the bottom. All readout modes and control registers use this coordinate system to set or change

modes of the chip.

Readout starts at the bottom of the pixel-field and continues towards up, row by row.

The internal readout of a row is split in two sections: first all even pixels; second all odd pixels. Later on the TCMI interface presents the

row in the regular order with even and odd pixels mixed.

E O E O

dummy pixels

Top

Pixel Field

R65

effective columns

Data out buffer: even & odd pixels; 160 x (12 bit DATA + SAT flag)

E O E O

E O

ADC: even or odd pixels; 80 x (12 bit DATA + SAT flag)

pixel

coordinates

Temp. sensor

dummy pixels

readout columns

Figure 29: pixel-field coordinates with row and column numbering scheme

(top-view, solder balls are bottom side)

5.7.2. Pixel architecture

The pixels are placed in groups 2x2 pixels, called herein “pixel group”. The pixel group performs two basic operations: Measurement (inte-

gration) and readout (ADC). Pixels are named as UE (Upper-row, Even-column), UO (Upper-row, Odd-column), LE (Lower-row, Even-col-

umn) and LO (Lower-row, Odd-column) depending on their location within the pixel group (see Figure 29). Pixels with the same name are

controlled simultaneously in the whole pixel-field. More precisely, pixels in the upper and lower rows are controlled simultaneously during

measurement, pixels in the even and odd columns are controlled simultaneously during readout.

The pixel group architecture allows the epc635 to operate the pixel-field in different modes and in combinations thereof according the fol-

lowing chapters.

Characteristics subject to change without notice

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