EPC635 datasheet(15/97 Pages) EPC

15 / 97 page

3.4. PCB design and SMD manufacturing process considerations

As the epc635 chip comes in a very small 44 pin chip scale package, the PCB layout should be made with special care. Because the sili -

con chip is small and light weight compared the the solder balls, it is highly recommended that all tracks to the chip should come straight

from the side. A symmetrical design is highly recommended to achieve high production yield.

The pads and the tracks should also have exactly the same width and shall be covered by a solder resist mask in order to avoid drain of

the solder tin alloy to the track.

Analog ground plane

fully covered with solder stop

Track:

0.150

Pad:

 0.250

Solder stop

covers PCB

and tracks

Pitch: 0.500

Solder stop opening:

 0.350

Vias must be filled solid or covered by solder mask

to prevent drain of underfill into or through the vias

Important Note

Due to the thin chip substrate,

unevenness of the substrate surface

will be visible on the top surface of

the chip. This may cause optical issues

and has to be considered carefully.

Figure 10: Recommended PCB layout (all measures in mm)

As shown in Figure 10, a ground plane shall be placed on the top PCB layer underneath the chip. This ground plane acts as a shield to

suppress high frequency emission of fast interface signal lines. It is important that this plane is completely flat. Thus, the plane must not be

scattered nor divided into sections. It should be rather full-faced and no via should be placed in this plane. Otherwise chip bending might

occur.

Underfill of the components reduces stress to the solder pads caused by e.g. temperature cycling or mechanical bending.Furthermore the

thermal and mechanical fatigue will be reduced and the longterm reliability will be increased. Underfill material and underfill selection is ap-

plication specific. It shall follow JEDEC-STD JEP150: Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assem-

bled Solid State Surface- Mount Components.

Please also, refer to the application note AN08 Process-Rules CSP Assembly which can be downloaded from the ESPROS website at

www.espros.com/application-notes. Obeying these recommendations a high manufacturing yield can be achieved.

3.5. Soldering and IC handling

Because the epc635 chip is only 50μm thick, a careful handling during the assembly process shall be assured in order to avoid mechanical

damage. In addition to that, careful PCB layout is needed in order to achieve reliable assembly results with a high yield. Please refer to the

application note AN08 from ESPROS which contains comprehensive information to these topics. This application note can be downloaded

at www.espros.com/application-notes.

Characteristics subject to change without notice

15 / 97

Datasheet_epc635-V1.02

EPC635 数据表(PDF) 15 Page - Espros Photonics corp

EPC635 数据表(HTML) 15 Page - Espros Photonics corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

数据表下载