EPC635 datasheet(38/97 Pages) EPC

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Continuous clock mode

This mode is selected by I2C_TCMI_control.tcmi_dclk_mode = 0. The frames are transmitted at high-speed using all *SYNC (VSYNC_A0,

HSYNC_A1, XSYNC_SAT_CFG), DATA[7:0] and DCLK outputs (Figure 34).

The DCLK signal toggles continuously.

All *SYNC*, DATA[7:0] signals are synchronously updated with the positive edge of the DCLK signal when its polarity is set as active-high;

with the negative edge of the DCLK signal when its polarity is set as active-low. The non-active edge of the DCLK output can be used by

the receiving end (application CPU) as a sampling clock. It should approximately be in the center of the data.

By using the default configuration, the active states of VSYNC_A0 and HSYNC_A1 signals indicate blanking periods during the frame

transmission. It is a legacy feature from the ITU-R 656 standard for video signal transmission. While DCLK toggles continuously, any data

during the blanking periods are not valid and must be ignored.

As soon as the measurement result of the first row of the new frame is available, VSYNC_A0 and HSYNC_A1 are set consecutively with

the next active edge of DCLK. VSYNC_A0 is active from the start until the end of the each complete frame. Whereas, HSYNC_A1 indi -

cates the validity of the DATA[7:0] and XSYNC_SAT_CFG (saturation bit) from the start until the end of a row.

By default, the XSYNC_SAT_CFG pin is used for the saturation bit. Optionally, it can be programmed to indicate the end of a frame

(tcmi_xsync_sat_sel = 0).

Frames

SHUTTER

Continuous clock: DCLK is running all the time

VSYNC

HSYNC

DCLK

Blanking

Valid data

Blanking

Conversion

R65 even

Data out

R65 1st

Conversion

R65 odd

Data out

R65 2nd

Conversion

R64 even

Conversion

R64 odd

Data out

R6 1st

Data out

R6 2nd

Integration

Init

Conversion

R6 odd

Integration

Init

Pro...

DATA[7:0] & SAT

1st DCS frame of the measurement cycle

Last DCS frame of the measurement cycle

Processing

Conversion

R63 even

Conversion

R6 odd

Conversion

R6 even

Data out

R7 2nd

Data out

R7 1st

Data out

R64 1st

Valid data

Blanking

Measurement cycle with selected number of DCS frames

Data out

R65 2nd

Valid data

Figure 34: Continuous clock mode

Gated clock mode

This mode is selected by I2C_TCMI_control.tcmi_dclk_mode = 1. The frames are transmitted at high-speed using only the DATA and

DCLK outputs (Figure 35). This allows the interfacing to embedded processors with standard parallel GPIOs. The external application

should calculate begin/end of the frame/row timing before starting the acquisition.

DCLK signal is generated only during non-blanking/valid data periods (corresponds to HSYNC_A1 inactive). Its frequency is same as in

the other mode. The DCLK toggle duration can be programmed to run few more cycles than HSYNC_A1 is active effectively. This allows

the external processor to finish its last operations with its FIFO/DMA.

All *SYNC* signals do not toggle in this mode, but can be optionally enabled.

All *SYNC* (optional), DATA[7:0] signals are synchronously updated with the positive edge of the DCLK signal when its polarity is set as

active-high; with the negative edge of the DCLK signal when its polarity is set as active-low. The non-active edge of the DCLK output can

be used by the receiving end (application CPU) as a sampling clock. It should approximately be in the center of the data.

Frames

SHUTTER

VSYNC

HSYNC

DCLK

Data not valid

Valid data

Conversion

R65 even

Data out

R65 1st

Conversion

R65 odd

Data out

R65 2nd

Conversion

R64 even

Conversion

R64 odd

Data out

R6 1st

Data out

R6 2nd

Integration

Init

Conversion

R6 odd

Integration

Init

Pro...

DATA[7:0] & SAT

1st DCS frame of the measurement cycle

Last DCS frame of the measurement cycle

Processing

Conversion

R63 even

Conversion

R6 odd

Conversion

R6 even

Data out

R7 2nd

Data out

R7 1st

Data out

R64 1st

Valid data

Measurement cycle with selected number of DCS frames

Clock

Data out

R64 2nd

Valid data

Clock

Figure 35: Gated clock mode

Characteristics subject to change without notice

38 / 97

Datasheet_epc635-V1.02

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