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EPC635 数据表(PDF) 61 Page - Espros Photonics corp |
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EPC635 数据表(HTML) 61 Page - Espros Photonics corp |
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61 / 97 page  7.7. Power saving options The epc635 has different power consumption depending on its activity level, see chapter 5.10., Power consumption levels. For power criti- cal applications e.g. battery powered systems, it is possible to enforce the epc635 to go in so-called power saving states. The different power saving modes and their description are listed in Table 37. Operating mode Power Time Description Shutdown Recovery [mW] [ms] [ms] INTEGRATION 270 TBD TBD Maximum average power consumption during regular 3D TOF operation READY (Idle) 170 TBD TBD Minimum average power consumption during regular 3D TOF operation SW POWER DOWN TBD TBD TBD Note: Only during regular READY mode possible. Power consumption during unnecessary functions where switched-off off by register commands. HW POWER DOWN TBD TBD TBD Power consumption during Pin 55 RESET = 0. Table 37: Power modes Table 38 is a help for the electronic designer and list the current consumption versus the power saving level and per supply level. Current Description Mode Units INTEGRATION READY SW POWER DOWN HW POWER DOWN IVDD Digital supply current 11 9 TBD TBD mA IVDDPLL PLL supply current 6 6 TBD TBD mA IVDDIO IO supply current 16 16 TBD TBD mA IVDDA Analog supply current 33 17 TBD TBD mA IVDDPXH Pixel analog 2 supply current 2 2 TBD TBD mA IVBS Bias supply current -2 -2 TBD TBD mA Table 38: Current consumption during power modes Is the epc635 during regular operation in the READY state, the SW POWER DOWN mode can be activated by the following command se - quence listed Table 39. No. Register Description Name Address Value 1 Regular 3D TOF operation 2 Power_Control (analog) 0xA5 0x00 Switch off of unnecessary supplies 3 CLK_enables 0x80 0x00 Switch off of unnecessary clocks 4 CFG_Mode_Control 0x7D 0x14 Switch system clock to XTAL clock 5 CFG_Mode_Control 0x7D 0x10 Switch off PLL 6 SW POWER DOWN 7 CFG_Mode_Control 0x7D 0x14 Switch on PLL 8 Wait > 32μs Wait until PLL stable 9 CFG_Mode_Control 0x7D 0x04 Switch system clock to PLL 10 CLK_enables 0x80 0x3F Switch on the clocks again 11 Power_Control (analog) 0xA5 0x07 Switch on the supplies again 12 Wait until supplies are stable 13 Regular 3D TOF operation Table 39: Sequence for the SW POWER DOWN mode © 2017 ESPROS Photonics Corporation Characteristics subject to change without notice 61 / 97 Datasheet_epc635-V1.02 www.espros.com |
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