EPC635 datasheet(46/97 Pages) EPC

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Memory space estimation:

The data-out operation transfers effectively 160x60pixel x 13bits/pixel (12 bit DATA + 1 bit SAT) = 124'800 bits (125kBit) pixel data with

each frame via the TCMI interface.

In a typical application with a CPU having a high-speed parallel interface (GPIO, CPI, CMI, etc.), each 13 bit sample is packed into a 2-

byte word, then stored in the application's frame buffer (internal SDRAM of the CPU or external SDRAM bridged via CPU). In that case, a

burst (1 row) makes 320 bytes. The frame acquisition including all rows/columns requires a storage space maximum of 19'200 bytes or

around 19kbyte per frame (1 kbyte = 1'024 bytes). For the 3D TOF distance measurements with 4 DCS, the application frame buffer must

be large enough to accommodate at least 4 DCS frames plus (may be) another 1 DCS frame size to store back the calculated distance

data. For a smooth SW programming, doubling this space is highly recommended as a bare minimum for the application frame buffer size.

This corresponds to a total of 2 x (4 + 1) x 19 kbytes = 190kbytes memory space. In practice, this can be realized with a single 256 kByte

SDRAM. Depending on the complexity of the application SW, this size must be increased.

5.9.7. Example applications of CPU architectures for high-speed frame data transfer

Several possible application CPU, DSP, FPGA configurations can be used with the epc635. Here are two architectures proposed as ex-

amples, to give the application developer a high-level overview.

The first one is a completely symmetric, non-blocking application frame buffer CPU architecture with a high-throughput imager to applica-

tion frame buffer data transfer concept. While the frame is continuously acquired, the current frame data is streamed from the epc635 to

the application frame buffer A. At the same time,the CPU can access and calculate the previously acquired data from the application frame

buffer B. The next frame, the memory channels are dynamically swapped between epc635 and the CPU by re-configuring the DMA chan-

nels. As there are two physically identical, separated memory channels, both transfers can flawlessly happen at the same time (see Figure

44).

DCLK

SHUTTER

XSYNC_SAT_CFG

HSYNC_A1

VSYNC_A0

DATA[7:0]

CPU / DSP

FIFO / DMA A

FIFO / DMA B

Frame A – Calc. Distance

Frame A - DCS3

Frame A - DCS2

Frame A - DCS1

Frame A - DCS0

Appl. frame buffer A

128kByte SDRAM

Frame B – Calc. Distance

Frame B - DCS0

Frame B - DCS1

Frame B - DCS2

Frame B - DCS3

Appl. frame buffer B

128kByte SDRAM

D-

D+

Application

Int. frame buffer C

128 – 512kByte SRAM

ARM / DSP Core

128kByte SRAM, Prog.

- Calc. Distance (3D)

- Cal. black & white (2D)

- Ctrl. INTs & DMAs

- Ctrl. epc635 via I2C & GPIO

- Ctrl. USB link with PC

- House keeping

App. CPU

Appl. program memory

512kByte FLASH, serial

SDA

SCL

epc635

Figure 44: Symmetric, non-blocking application frame buffer CPU architecture

Characteristics subject to change without notice

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Datasheet_epc635-V1.02

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