EPC635 datasheet(91/97 Pages) EPC

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I2C_TCMI_control

I2C and TCMI register, SEG4 *: Control

0xCB

Bit No.

Bit name

reserved

tcmi_8bit_

data_sat_en

tcmi_data_format_sel

tcmi_dclk

_mode

tcmi_esm_en

i2c_spike

_filter_en

i2c_clock

_stretch_en

Operation

Default

0x23

tcmi_8bit_

data_sat_en:

When split modes selected (tcmi_data_format_sel = 11 or 10), forces bit DATA[0] of the LSByte = 1 when the

pixel is saturated. Not effective with other TCMI data formats.

0: disabled

1: enabled

tcmi_data_format_sel: TCMI 8/12-bit data format select

00: reserved

01: 8-bit mode:

Transfers the 8 MSB bits of the pixel data with 1x DCLK.

10: lsb/msb split mode:

Transfers 12 bit pixel data with LSByte leading and MSByte trailing with 2x DCLK.

Data are MSB aligned (default). The optional SAT bit is on the LSB.

11: msb/lsb split mode

Transfers 12 bit pixel data with MSByte leading and LSByte trailing with 2x DCLK.

Data are MSB aligned. The optional SAT bit is on the LSB.

tcmi_dclk_mode:

TCMI DCLK mode select

0: continuous

1: gated

tcmi_esm_en:

TCMI ESM mode enable

0: disabled

1: enabled

i2c_spike_filter_en:

I2C pins input spike filter

0: disabled (> 1MHz)

1: enabled (≤ 1MHz, FM+)

i2c_clock_stretch_en: I2C clock stretching

0: disabled

1: enabled

Note:

When i2c_spike_filter_en = 0, SDA and SCL pins can be used up to 10MHz as inputs (driven rail-to-rail by a real CMOS driver,

no pull-up). They can be used up to 2MHz as outputs.

Characteristics subject to change without notice

91 / 97

Datasheet_epc635-V1.02

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