EPC635 datasheet(37/97 Pages) EPC

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5.9. TOF camera interface (TCMI)

The TOF Camera Module Interface (TCMI) is a programmable high-speed parallel data output interface to down-load the pixel data.

The TCMI interface provides:

■ Programmable active high/low logic levels on all clock and control signals individually (default: all active high).

■ Programmable output clock rates.

■ 12-bit parallel output with 1 bit saturation flag transferred in two bytes on TCMI interface.

■ The output data format is programmable: 12-bit mode, lsb/msb split mode, msb/lsb split mode, 8-bit mode.

■ Programmable 'ITU-R 656 like' synchronization options which allows easy connection to a wide variety of high-performance low-cost

SoC embedded processors. It supports hardware synchronization, but not embedded 0xFF/0x00 sync data packets.

When the integration period is terminated and ADC conversion is finished, the readout results are moved into the data out buffers to be im-

mediately transmitted via the TCMI interface. The conversion of one row takes in total 31.5µs.

Depending of the mode selection (4x DCS, 2x DCS, ...) a programmable number of DCS frames are generated by the epc635. The gener-

ated data is streamed out as a complete block of 1 DCS frame, one after the other following the procedure described in chapter 5.7. Each

row contains 12-bit DCS values and the SAT bit.

The pixel values are streamed out as 12 bit signed numbers. The rows are streamed out in sequence from the bottom to the top e.g.

R65 (C4, C5, … C163), R64 (C4, C5, … C163) and so on until R6 (C4, C5, … C163). The stream-out of one row takes 16µs with default

clock settings (40MHz TCMI clock rate).

The transfer of a DCS frame should not be interrupted or stopped, once it is started. The application should have enough bandwidth to re -

ceive all transmitted frames.

IMPORTANT:

Refer to chapter 8.7.21. for setting correct data format 2's complement integer (tcmi-data-polarity).

The application software must take care about the negative (-) single ended sample value, accordingly.

5.9.1. TCMI clock mode

The TCMI supports two clock modes: Continuous clock (default) and gated clock. Both modes use internal tcmi_clk as a time base. The

user must program the appropriate clock speed before running the TCMI. It sets the output data transfer rate (refer to signal DCLK).

The frequency is programmable to 10, 20, 40, 80MHz. The user application is responsible to set the correct clock rate in order to achieve

the most efficient data acquisition throughput for the target application. The choice depends on user system factors such as e.g. applica-

tion CPU/DSP's GPIO and/or bus speeds.

tcmi_clk_div (0x89)

10MHz DCLK

20MHz DCLK

40MHz DCLK

80MHz DCLK

[#]

2 (default)

Table 16: DCLK settings

Characteristics subject to change without notice

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Datasheet_epc635-V1.02

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