AD9656EBZ datasheet(32/47 Pages) AD

32 / 47 page

Data Sheet

AD9656

Rev. A | Page 31 of 46

Most of the synchronization features of the JESD204B interface

are enabled by default for typical applications. In some cases,

these features can be disabled or modified as follows:

•

ILAS enabling is controlled in Register 0x5F, Bits[3:2] and

is enabled by default. Optionally, to support some unique

instances of the interfaces (such as NMCDA-SL), the

JESD204B interface can be programmed to either disable the

ILAS sequence or continually repeat the ILAS sequence.

The AD9656 has fixed values for some JESD204B interface

parameters, and they are as follows:

•

[N’] = 16: number of bits per sample is 16, in Register 0x73,

Bits[4:0]

•

[CF] = 0: number of control words/frame clock

cycle/converter is 0, in Register 0x75, Bits[4:0]

Verify read only values: lanes per link (L), octets per frame (F),

number of converters (M), and samples per converter per frame

(S). The AD9656 calculates values for some JESD204B parameters

based on other settings, particularly the quick configuration

the register map for verification:

•

[L] = lanes per link can be 1, 2 or 4; read the values from

•

[F] = octets per frame can be 2, 4, or 8; read the value from

•

[HD] = high density mode is 0; read the value from

•

[M] = number of converters per link; default is 4, but can

be 1, 2, or 4. Read the value from Register 0x71, Bits[7:0]

•

[S] = samples per converter per frame is 1; read the value

from Register 0x74, Bits[4:0]

Check FCHK, Checksum of JESD204B Interface Parameters

The JESD204B parameters can be verified through the checksum

value [FCHK] of the JESD204B interface parameters. Each lane has

a FCHK value associated with it. The FCHK value is transmitted

during the ILAS second multiframe and can be read from the

internal registers.

The checksum value is the modulo 256 sum of the parameters

listed in the No. column of Table 14. The checksum is calculated

by adding the parameter fields before they are packed into the

octets shown in Table 14.

The FCHK for the lane configuration for data exiting Lane 0

can be read from Register 0x78. Similarly, the FCHK for the lane

configuration for data exiting Lane 1 can be read from Register

0x79, FCHK for Lane 2 can be read from Register 0x7A, and

FCHK for Lane 3 can be read from Register 0x7B.

Table 14. JESD204B Configuration Table Used in ILAS and

CHKSUM Calculation

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Set Additional Digital Output Configuration Options

Other data format controls include the following:

•

Invert polarity of serial output data: Register 0x60, Bit 1

•

ADC data format (offset binary or twos complement):

•

Options for interpreting signals on the SYSREF± and

SYNCINB± pins: Register 0x3A, Bits[4:3]

•

Option to remap converter (logical lane) and SERDOUTx±

(physical lane) assignments: Register 0x82 and Register 0x83.

See Figure 68 for a simplified conceptual block diagram.

Reenable Lanes After Configuration

After modifying the JESD204B link parameters, enable the link so

that the synchronization process can begin. This is accomplished

by writing Logic 0 to Register 0x5F, Bit 0.

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