AD9656EBZ datasheet(11/47 Pages) AD

部件名	AD9656EBZ

功能描述	Quad, 16-Bit, 125 MSPS 1.8 V Analog-to-Digital Converter

PDF	47 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

标志

11 / 47 page

AD9656

Data Sheet

Rev. A | Page 10 of 46

Timing Diagrams

Refer to the Memory Map Register Table section for SPI register settings.

VINA+/

VINA–

VINB+/

VINB–

VINC+/

VINC–

VIND+/

VIND–

CLK+

CLK–

SERDOUTx+

CLK+

CLK–

SERDOUTx–

VINB, SAMPLE N – 23,

MSB FIRST, 8B/10B

ENCODED DATA

VINC, SAMPLE N – 23,

MSB FIRST, 8B/10B

ENCODED DATA

VIND, SAMPLE N – 23,

MSB FIRST, 8B/10B

ENCODED DATA

VINA, SAMPLE N – 23,

MSB FIRST, 8B/10B

ENCODED DATA

SAMPLE N

N – 23

N – 21

N – 22

N + 1

N – 1

N – 20

SAMPLE N

N – 23

N – 21

N – 22

N + 1

N – 1

N – 20

SAMPLE N

N – 23

N – 21

N – 22

N + 1

N – 1

N – 20

SAMPLE N

N – 23

N – 21

N – 22

N + 1

N – 1

N – 20

N – 19

Figure 2. Data Output Timing, M = 4, L = 1

tREFS

CLK+

CLK–

SYSREF–

SYSREF+

tREFH

Figure 3. SYSREF± Setup and Hold Timing (Clock Divider = 1)

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