Data Sheet

AD9656

Rev. A | Page 9 of 46

Temperature

Min

Typ

Max

Unit

At 6.4 Gbps

25°C

8

ps

At 6.4 Gbps

25°C

1.25

ps rms

Output Rise Time/Fall Time

25°C

50

ps

Differential Termination Resistance

25°C

100

Ω

APERTURE

25°C

1

ns

25°C

135

fs rms

Out of Range Recovery Time

25°C

1

Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

The clock divider can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4

Maximum conversion rate is with the AD9656 not limited by the maximum allowable output data rate. See the Digital Outputs and Timing section for information on

conditions when the conversion rate is limited by the maximum allowable output data rate.

5

Refer to Figure 3 for timing diagram.

6

Typical PLL lock time at 125 MSPS (24 μs + 7680 sample clock periods)

7

Time required for the ADC to return to normal operation from power-down mode.

8

Time required for the JESD204B output to return to normal operation from power-down mode at 125 MSPS (PLL lock time + 13 sample clock periods)

9

Delay required for SYNCINB rising edge/Rx CGS start. See Figure 66.

10

ADC conversion rate cycles.

TIMING SPECIFICATIONS

Table 7.

Parameter

Description

Limit

Unit

SPI TIMING REQUIREMENTS

See Figure 74

Setup time between the data and the rising edge of SCLK

2

ns min

Hold time between the data and the rising edge of SCLK

2

ns min

Period of the SCLK

40

ns min

Setup time between CSB and SCLK

2

ns min

Hold time between CSB and SCLK

2

ns min

SCLK pulse width high

10

ns min

SCLK pulse width low

10

ns min

Time required for the SDIO pin to switch from an input to an output relative to the

SCLK falling edge (not shown in Figure 74)

10

ns min

Time required for the SDIO pin to switch from an output to an input relative to the

SCLK rising edge (not shown in Figure 74)

10

ns min