AD9656EBZ datasheet(22/47 Pages) AD

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Data Sheet

AD9656

Rev. A | Page 21 of 46

THEORY OF OPERATION

The AD9656 is a multistage, pipelined ADC. Each stage

provides sufficient overlap to correct for flash errors in the

preceding stage. The quantized outputs from each stage are

combined into a final 16-bit result in the digital correction

logic. The serializer transmits this converted data in a 16-bit

output. The pipelined architecture permits the first stage to

operate with a new input sample while the remaining stages

operate with the preceding samples. Sampling occurs on the

rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter [MDAC]). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and data clocks.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9656 is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

CPAR

CSAMPLE

CPAR

VINx–

VINx+

Figure 46. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 46). When the input

circuit is switched to sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each input

can help reduce the peak transient current injected from the

output stage of the driving source. In addition, low Q inductors or

ferrite beads can be placed on each leg of the input to reduce high

differential capacitance at the analog inputs and therefore achieve

the maximum bandwidth of the ADC. Such use of low Q inductors

or ferrite beads is required when driving the converter front end at

high IF frequencies.

Either a differential capacitor or two single-ended capacitors can

be placed on the inputs to provide a matching passive network.

This ultimately creates a low-pass filter at the input to limit

unwanted broadband noise. See the AN-742 Application Note, the

AN-827 Application Note, and the Analog Dialogue article

“Transformer-Coupled Front-End for Wideband A/D Converters”

for more information. In general, the precise values depend on

the application.

Input Common-Mode Voltage

The analog inputs of the AD9656 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide

this bias externally. Setting the device so that VCM = AVDD/2 is

recommended for optimum performance, but the device can

function over a wider VCM range with reasonable performance,

as shown in Figure 47 and Figure 48.

100

110

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

VCM (V)

SNR (dBFS)

SFDR (dBc)

Figure 47. SNR/SFDR vs. Common-Mode Voltage (VCM),

fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V

100

110

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

VCM (V)

SFDR (dBc)

SNR (dBFS)

Figure 48. SNR/SFDR vs. Common-Mode Voltage (VCM),

fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V

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