AD9656EBZ datasheet(30/47 Pages) AD

30 / 47 page

Data Sheet

AD9656

Rev. A | Page 29 of 46

JESD204B Synchronization Details

The AD9656 is a JESD204B Subclass 1 device and establishes

synchronization of the link through two control signals (SYSREF

and SYNCINB). At the system level, multiple converter devices are

aligned using a common SYSREF signal and device clock (CLK).

The synchronization process is accomplished over three phases:

code group synchronization (CGS), initial lane alignment sequence

(ILAS), and data transmission. If scrambling is enabled, the bits are

not scrambled until the data transmission phase. The CGS phase

and ILAS phase do not use scrambling.

CGS Phase

The assertion of the SYNCINB signal by the JESD204B Rx for

more than 5 frames and 9 octets informs the JESD204B Tx to

synchronize. To have the AD9656 to respond by initiating the

CGS phase, the SYNCINB signal must be asserted for at least 4

LMFC cycles if no SYSREF realignment is required. As illustrated

in Figure 66, if SYSREF realignment is needed, the SYNCINB

signal must be asserted for at least 6 LMFC cycles. In the CGS

phase, the JESD204B transmit block transmits /K28.5/ characters.

The receiver (external logic device) must find K28.5 characters

in the input data stream using clock and data recovery (CDR)

techniques.

When a certain number of consecutive K28.5 characters are

detected on the link lanes, the receiver initiates a SYSREF edge

so that the AD9656 transmit data establishes a LMFC internally.

The SYSREF edge also resets any sampling edges within the

ADC to align sampling instances to the LMFC. This is important

to maintain synchronization across multiple devices.

The receiver or logic device deasserts the SYNCINB signal applied

to the SYNCINB± pin according to the previously stated timing

requirements.

ILAS Phase

The ILAS phase begins on the second LMFC boundary after

SYNCINB is deasserted; and the ILAS phase contents are as

illustrated in Figure 67. The transmitter sends out the ILAS

according to the JESD204B standard, and the receiver aligns

all lanes of the link and verifies the parameters of the link.

The ILAS phase lasts for four multiframes and includes the

following:

•

Multiframe 1: Begins with an /R/ character [K28.0] and

ends with an /A/ character [K28.3].

•

Multiframe 2: Begins with an /R/ character followed by a

/Q/ [K28.4] character, followed by link configuration

parameters over 14 configuration octets (see Table 12),

and ends with an /A/ character.

•

Multiframe 3: same as Multiframe 1.

•

Multiframe 4: same as Multiframe 1.

During the transmission of the ILAS, all data that is not a K28

control character or a configuration parameter is a repeating ramp

pattern from 0 to 255. In the default state (M = 4, L = 1, K = 32),

there are 256 octets per multiframe, which allows the ramp to

complete within Multiframe 1, 3, and 4. For configurations with

less than 256 octets per multiframe, the ramp continues to rise into

the next multiframe. Multiframe 2 has 14 configuration octets

following a /Q/ character that is transmitted instead of ramp

values. The ramp continues to advance internally while the 14

configuration octets are transmitted and ramp values appear

again after the 14 configuration octets end.

ILAS

USER DATA

CGS

DATA

LMFC

K = CGS CNTL. CHAR.

R = START OF MULTIFRAME.

A = END OF MULTIFRAME.

Q = START OF LINK CFG DATA

LINCFG DATA

K K K R 0 1

2...253

A R Q C...C 15...253 A R

0...253

A R

0...253

A SAMPLE DATA...

Figure 67. ILAS Data Sequence, M = 4, L = 1, K = 32

AD9656EBZ 数据表(PDF) 30 Page - Analog Devices

AD9656EBZ 数据表(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载