AD9656EBZ datasheet(28/47 Pages) AD

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Data Sheet

AD9656

Rev. A | Page 27 of 46

JESD204B Configurations

Figure 68 shows a simplified conceptual block diagram of the

AD9656 JESD204B link. By default, the AD9656 is configured

to use four converters and one lane. The AD9656 allows for other

configurations such as combining the outputs of two of the four

converters onto a single lane resulting in the data from the four

converters being output on two lanes. The mapping of the 0, 1,

2, and 3 digital output paths can be changed. These modes are

set up through a quick configuration register in the SPI register

map, along with additional customizable options.

By default in the AD9656, the 16-bit word from each converter

is divided into two octets (8 bits of data each). Bit 0 (MSB)

through Bit 7 are in the first octet and Bit 8 through Bit 15 (LSB)

are the second octet.

The two resulting octets can be scrambled. Scrambling is

optional; however, it is available to avoid spectral peaks when

transmitting similar digital data patterns. The scrambler uses a

self synchronizing, polynomial-based algorithm defined by the

equation 1 + x14 + x15. The descrambler in the receiver must be a

self synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8b/10b encoder. The

8b/10b encoder works by taking eight bits of data (an octet) and

encoding them into a 10-bit symbol. Figure 69 shows how the

16-bit data is output from the ADC, the two octets are scrambled,

and how the octets are encoded into two 10-bit symbols. Figure 69

illustrates the default data format.

At the data link layer, in addition to the 8b/10b encoding,

character replacement allows the receiver to monitor frame

alignment. The character replacement process occurs on the frame

and multiframe boundaries, and implementation depends on

which boundary is occurring and if scrambling is enabled.

If scrambling is disabled, the following applies. If the last scrambled

octet of the last frame of the multiframe equals the last octet of

the previous frame, the transmitter replaces the last octet with

the control character /A/ = /K28.3/. On other frames within the

multiframe, if the last octet in the frame equals the last octet of

the previous frame, the transmitter replaces the last octet with

the control character /F/= /K28.7/.

If scrambling is enabled, the following applies. If the last octet of

the last frame of the multiframe equals 0x7C, the transmitter

replaces the last octet with the control character /A/ = /K28.3/.

On other frames within the multiframe, if the last octet equals

0xFC, the transmitter replaces the last octet with the control

character /F/ = /K28.7/.

Refer to JEDEC Standard No. JESD204B (July 2011) for additional

information about the JESD204B interface. Section 5.1 covers

the transport layer and data format details, and Section 5.2 covers

scrambling and descrambling.

Initial JESD204B Link Startup

The power-on default JESD204B state of the AD9656 is M4L1.

Once the ADC is configured and the appropriate clocks are

provided, any JESD204B parameters different from the default

configuration must be set prior to enabling the link. Figure 65

depicts the start-up and synchronization timing of the AD9656

JESD204B Tx in subclass 1 mode. It is recommended that the

SYNCINB signal (defined as SYNC~, according to the JESD204B

standard) is asserted at power-up and must not be deasserted

until after SYSREF has been applied according to the timing

illustrated in the figure. Once the PLL has settled the serial outputs

on each lane, begin to toggle between 1’s and 0’s. Shortly thereafter

(13 frame clock cycles), K28.5 characters are sent across the link

on each lane and the local multiframe clock (LMFC) is generated.

At this time SYSREF can be applied.

SYSREF

SYNCINB

POWER ON

PLL LOCKED

13 FRAMES

DATA OUT

LMFCADC

SYNCINB DEASSERT

K28.5

ILAS

K28.5

0101..

24µs + 7680

SAMPLE CLOCKS

120µs TOTAL AT 80MHz

< 2 LMFCs FOR

STABLE LMFC

AFTER SYSREF

ILAS STARTS ON

SECOND LMFC

AFTER SYNCINB

DEASSERT

DEASSERT SYNCINB

ON SECOND LMFC

AFTER SYSREF

Figure 65. JESD204B Tx Start-Up and Synchronization Timing

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