AD9656EBZ datasheet(29/47 Pages) AD

29 / 47 page

AD9656

Data Sheet

Rev. A | Page 28 of 46

Resynchronization

Figure 66 depicts the resynchronization timing for the AD9656

JESD204B interface. When the subclass 1 receiving logic device

is ready to resynchronize, it asserts the SYNCINB signal and

issues a SYSREF request. Note that once SYSREF is applied, the

JESD204B internal clocks are reset and take up to 2 LMFC

periods to fully settle.

Once the new phase of LMFC is stable, SYNCINB must remain

asserted for at least four LMFC cycles for the AD9656 to respond

by sending the K28.5 characters. This commences the CGS portion

of subclass 1 synchronization. Once the Tx deasserts the SYNCINB

signal, the ILAS starts on the second LMFC boundary.

SYSREF REQUEST

(ASSERT SYNCINB)

START OF

SYSREF

START CGS

SYNCINB

DEASSERT

SYSREF

SYNCINB

DATA OUT

LMFCADC

< 2 LMFCs FOR

STABLE LMFC

AFTER SYSREF

UP TO 6 LMFCs AFTER SYREF

RISING EDGE TO START CGS

ILAS START ON SECOND LMFC

AFTER SYNCINB DEASSERT

ADC DATA

K28.5

ILAS

Figure 66. JESD204B Tx Resynchronization Timing

AD9656EBZ 数据表(PDF) 29 Page - Analog Devices

AD9656EBZ 数据表(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载