AD9656EBZ datasheet(31/47 Pages) AD

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AD9656

Data Sheet

Rev. A | Page 30 of 46

Table 12. 14 Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Reserved, don’t care (RES1)

Reserved, don’t care (RES2)

FCHK[7:0]

Data Transmission Phase

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:

•

If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.

•

If scrambling is enabled and the last octet of the

multiframe is equal to 0x7C, or the last octet of a frame is

equal to 0xFC.

Link Setup Parameters

The following demonstrates how to configure the AD9656

JESD204B interface. The steps to configure the output include

the following:

1. Disable the lanes before changing configuration.

2. Select one quick configuration option.

3. Configure the detailed options.

4. Check FCHK, checksum of JESD204B interface parameters.

5. Set additional digital output configuration options.

6. Reenable the lane(s).

Disable Lanes Before Changing Configuration

Before modifying the JESD204B link parameters, disable the link

and hold it in reset. This is accomplished by writing Logic 1 to

Select Quick Configuration Option

Write to Register 0x5E, the JESD204B quick configuration

configuration options and resulting JESD204B parameter values.

•

0x41 = four converters, one lane

•

0x42 = four converters, two lanes

•

0x44 = four converters, four lanes

•

0x21 = two converters, one lane

•

0x22 = two converters, two lanes

•

0x11 = one converter, one lane

Configure Detailed Options

Configure the tail bits and control bits.

•

With N’ = 16 and N = 14 (nondefault configuration), two

bits are available per sample for transmitting additional

information over the JESD204B link. The options are tail

bits or control bits. By default, tail bits of 0b00 value are used.

•

Tail bits are dummy bits sent over the link to complete the

two octets and do not convey any information about the input

signal. Tail bits can be fixed zeros (default) or pseudo-

random numbers (Register 0x5F, Bit 6).

•

One or two control bits can be selected to replace the tail

bits using Register 0x72, Bits[7:6]. The meaning of the

control bits can be set using Register 0x14, Bits[7:5].

Set lane identification values.

•

JESD204B allows parameters to identify the device and

lane. These parameters are transmitted during the ILAS phase,

and they are accessible in the internal registers.

•

The three identification values are device identification

(DID), bank identification (BID), and lane identification

(LID). DID and BID are device specific; therefore, they can

be used for link identification.

Set the number of frames per multiframe, K.

•

Per the JESD204B specification, a multiframe is defined as a

group of K successive frames, where K is from 1 to 32, and

requires that the number of octets be from 17 to 1024. The

K value is set to 32 by default in Register 0x70, Bits[4:0].

Note that the K value is the register value plus 1.

•

The K value can be changed; however, it must comply with

a few conditions. The AD9656 uses a fixed value for octets

per frame (F) based on the JESD204B quick configuration

setting. K must also be a multiple of 4 and conform to the

following equation:

32 ≥ K ≥ Ceil (17/F)

•

The JESD204B specification also specifies that the number

of octets per multiframe (K × F) be from 17 to 1024. The F

value is fixed through the quick configuration setting to

ensure that this relationship is true.

Table 13. JESD204B Configurable Identification Values

DID Value

Value Range

LID (Lane 0)

0x66, [4:0]

0…31

LID (Lane 1)

0x67, [4:0]

0…31

DID

0x64, [7:0]

0…255

BID

0x65, [3:0]

0…15

Scramble, SCR.

•

Scrambling can be enabled or disabled by setting Register 0x6E,

Bit 7. By default, scrambling is enabled. Per the JESD204B

protocol, scrambling is functional only after the lane

synchronization has completed.

Select lane synchronization options.

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