AD9656

Data Sheet

Rev. A | Page 40 of 46

Addr

(Hex)

Register Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Notes/

Comments

0x5F

JESD204B Link

CTRL 1

Open

Tail bits

mode:

0 = fill

with 0s,

1 = fill with

9-bit PN

sequence

JTX

transport

layer test:

0 = not

enabled,

1 = long

transport

layer test

enabled

Multiframe

alignment

character

insertion:

0 =

disabled,

1 =

enabled

ILAS mode:

00 = ILAS disabled,

01 = ILAS enabled

(normal mode),

11 = ILAS always on (test mode)

Frame

alignment

character

insertion:

0 =

enabled,

1 =

disabled

0 = JTX

link

enabled,

1 = JTX

link

disabled

0x14

0x60

JESD204B Link

CTRL 2

Reserved

SYNCINB±

pin

invert:

0 = not

inverted,

1 =

inverted

SYNCINB±

pin input

bias:

0 =

disabled,

1 =

enabled

Open

Open

JTX output

invert:

0 =

normal,

1 =

inverted

Reserved

0x10

0x61

JESD204B Link

CTRL 3

Reserved

Reserved

Test data injection point:

01 = 10-bit data injected

at 8b/10b encoder output,

10 = 8-bit data at

scrambler input

JTX test mode patterns:

0000 = normal operation (test mode disabled),

0001 = alternating checkerboard,

0010 = 1/0 word toggle,

0011 = PN sequence PN23,

0100 = PN sequence PN9,

0101= continuous/repeat user test mode,

0110 = single user test mode,

0111 = reserved,

1000 = modified RPAT test sequence (8-bit data only),

1100 = PN sequence PN7,

1101 = PN sequence PN15,

other setting are unused

0x00

0x62

JESD204B Link

CTRL 4

Reserved

0x00

0x64

JESD204B DID

configuration

Device identification (DID) = C0

0xC0

Read only.

0x65

JESD204B BID

configuration

Open

Open

Open

Open

JTX bank identification (BID) number

0x00

0x66

JESD204B LID

Configuration 0

Open

Open

Open

JTX lane identification (LID) number for Lane 0

0x00

0x67

JESD204B LID

Configuration 1

Open

Open

Open

JTX lane identification (LID) number for Lane 1

0x01

0x68

JESD204B LID

Configuration 2

Open

Open

Open

JTX lane identification (LID) number for Lane 2

0x02

0x69

JESD204B LID

Configuration 3

Open

Open

Open

JTX lane identification (LID) number for Lane 3

0x03

0x6E

JESD204B

parameters,

SCR/L

JESD204B

scrambling

(SCR): 0 =

disabled,

1 =

enabled

Open

Open

JESD204B serial lane control:

0 = one lane per link (L = 1),

1 = two lanes per link (L = 2),

2 = unused,

3 = four lanes per link (L = 4),

4 to 31 = unused

0x80

0x6F

JESD204B

parameters, F

JESD204B number of octets per frame (F); calculated value, F = (2 × M)/L

0x00

Read only.

0x70

JESD204B

parameters, K

Open

Open

Open

JESD204B number of frames per multiframe (K); K = register contents + 1,

but also must be a multiple of four octets

0x1F

0x71

JESD204B

parameters, M

JESD204B number of converters (M): 0 = one converter (M = 1), 1 = two converters (M = 2), 3 = four converters (M = 4, default)

0x03

0x72

JESD204B

parameters,

CS/N

00 = number of

control bits

sent per sample (CS = 0)

Open

JTX converter resolution (N):

0x0F = 16-bit,

0x0D = 14-bit,

0x0B = 12-bit,

0x09 = 10-bit

0x0F

0x73

JESD204B

parameters,

subclass/Np

JESD204B subclass;

0x0 = Subclass 0;

0x1 = Subclass 1 (default)

JESD204B number of bits per sample (N’); N’ = register contents + 1

0x2F

0x74

JESD204B

parameters, S

Reserved

JESD204B converter samples per frame (S); S = register contents + 1

0x20

Read only.

0x75

JESD204B

parameters,

HD and CF

JESD204B

HD

value = 0

Open

Open

JESD204B control words per frame clock cycle per link (CF = 0, fixed)

0x00

Read only.

0x76

JESD204B

RESV1

JESD204B Serial Reserved Field No. 1 in link configuration, see Table 12 (RES1)

0x00

0x77

JESD204B

RESV2

JESD204B Serial Reserved Field No. 2 in link configuration, see Table 12 (RES2)

0x00

0x78

JESD204B

CHKSUM0

JESD204B serial checksum value in link configuration, see Table 12 for Lane 0 (FCHK)

Read only.