AD9656

Data Sheet

Rev. A | Page 8 of 46

Temperature

Min

Typ

Max

Unit

LOGIC INPUTS (CSB, PDWN, SCLK)

Logic 1 Voltage Range

Full

1.2

SVDD + 0.2

V

Logic 0 Voltage Range

Full

0

0.8

V

Input Resistance

25°C

26

kΩ

Input Capacitance

25°C

2

pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Range

Full

1.2

SVDD + 0.2

V

Logic 0 Voltage Range

Full

0

0.8

V

Input Resistance

25°C

26

kΩ

Input Capacitance

25°C

5

pF

Full

1.79

V

Full

0.05

V

DIGITAL OUTPUTS (SERDOUTx±)

Logic Compliance

Full

CML

Full

400

600

750

mV

Full

0.75

DRVDD/2

1.05

V

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for the SDIO pins on 13 individual AD9656 devices sharing the same connection.

SWITCHING SPECIFICATIONS

Table 6.

Parameter1, 2

Temperature

Min

Typ

Max

Unit

CLOCK3

Input Clock Rate

Full

40

1000

MHz

Conversion Rate4

Full

40

125

MSPS

Full

4.00

ns

Full

4.00

ns

SYNC Setup Time to Clock

Full

1.4

ns

SYNC Hold Time to Clock

Full

−0.4

ns

Full

370

600

ps

Full

−92

0

ps

DATA OUTPUT PARAMETERS

Data Output Period or Unit Interval (UI)

Full

Seconds

Data Output Duty Cycle

25°C

50

%

Data Valid Time

25°C

0.81

UI

25°C

86

µs

Wake-Up Time

Standby

25°C

250

ns

ADC (Power-Down)7

25°C

375

µs

Output (Power-Down)8

25°C

86

µs

SYNCINB Falling Edge to First K.28 Characters

Full

4

Multiframes

CGS Phase K.28 Characters Duration

Full

1

Multiframe

Subclass 1: SYSREF Rising Edge to First Valid K.28 Characters9

Full

5

6

Multiframe

Pipeline Delay

JESD204B M4, L1 Mode (Latency)

Full

23

Cycles10

JESD204B M4, L2 Mode (Latency)

Full

29

Cycles10

JESD204B M4, L4 Mode (Latency)

Full

44

Cycles10

Data Rate per Lane

Full

8.0

Gbps