AD9656EBZ datasheet(3/47 Pages) AD

3 / 47 page

AD9656

Data Sheet

Rev. A | Page 2 of 46

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications, VREF = 1.4 V.................................................. 3

DC Specifications, VREF = 1.0 V.................................................. 4

AC Specifications, VREF = 1.4 V .................................................. 5

AC Specifications, VREF = 1.0 V .................................................. 6

Digital Specifications ................................................................... 7

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 14

VREF = 1.4 V ................................................................................. 14

VREF = 1.0 V ................................................................................. 17

Equivalent Circuits ......................................................................... 20

Theory of Operation ...................................................................... 21

Analog Input Considerations ................................................... 21

Voltage Reference ....................................................................... 23

Clock Input Considerations...................................................... 24

Power Dissipation and Power-Down Mode ........................... 26

Digital Outputs ........................................................................... 26

Serial Port Interface (SPI).............................................................. 35

Configuration Using the SPI..................................................... 35

Hardware Interface..................................................................... 35

SPI Accessible Features.............................................................. 35

Memory Map .................................................................................. 37

Reading the Memory Map Register Table............................... 37

Memory Map Register Table..................................................... 38

Memory Map Register Descriptions........................................ 42

Applications Information .............................................................. 44

Design Guidelines ...................................................................... 44

Power and Ground Recommendations ................................... 44

Clock Stability Considerations ................................................. 44

Exposed Pad Thermal Heat Slug Recommendations............ 44

Reference Decoupling................................................................ 44

SPI Port ........................................................................................ 44

Outline Dimensions ....................................................................... 45

Ordering Guide .......................................................................... 45

REVISION HISTORY

3/2017—Rev. 0 to Rev. A

Changed DSYNC to SYNCINB, to SYSREF, DSYNC± to

SYNCINB±, and DSYSREF± to SYSREF±....................Throughout

Changes to Applications Section, General Description Section, and

Product Highlights Section................................................................ 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to AC Specifications, VREF = 1.4 V Section and Table 3 .... 5

Change to AC Specifications, VREF = 1.0 V Section ..................... 6

Changes to Worst Other Spur or Harmonic (Excluding Second

or Third) Parameter, Table 4, Digital Specifications Section,

and Table 5......................................................................................... 7

Changes to Table 6............................................................................ 8

Changes to Table 6 Endnotes .......................................................... 9

Changes to Figure 2 Caption ........................................................... 10

Change to Table 8 ........................................................................... 11

Changes to Table 10........................................................................ 12

Changes to Figure 39, Figure 41, Figure 41 Caption,

and Figure 44................................................................................... 20

Added Figure 42, Renumbered Sequentially .............................. 20

Changes to Input Clock Divider Section..................................... 25

Changes to Power Dissipation and Power-Down Mode Section...26

Change to JESD204B Transmit Top Level Description Section .....26

Added JESD204B Configurations Section Title, Initial JESD204B

Link Startup Section, and Figure 65..................................................27

Added Resynchronization Section and Figure 66.........................28

Changes to CGS Phase Section and ILAS Phase Section............29

Added Figure 67.......................................................................................29

Change to Set Additional Digital Output Configuration

Options Section........................................................................................31

Changes to Figure 68 and Figure 68.....................................................32

Changes to Digital Outputs and Timing Section and Figure 71.....33

Changes to Hardware Interface Section ..............................................35

Changes to Table 19.................................................................................39

Change to Transfer (Register 0xFF) Section...................................42

Changes to Resolution/Sample Rate Override (Register 0x100) ....43

Changes to Power and Ground Recommendations Section and

Clock Stability Considerations Section............................................44

12/2013—Revision 0: Initial Version

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