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AD9656EBZ 数据表(PDF) 13 Page - Analog Devices

部件名 AD9656EBZ
功能描述  Quad, 16-Bit, 125 MSPS 1.8 V Analog-to-Digital Converter
PDF  47 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9656EBZ 数据表(HTML) 13 Page - Analog Devices

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AD9656
Data Sheet
Rev. A | Page 12 of 46
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NIC = NOT INTERNALLY CONNECTED. CAN BE CONNECTED TO GROUND IF DESIRED.
2. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
3. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AVDD
VIND+
VIND–
AVDD
AVDD
CLK–
CLK+
AVDD
SYSREF+
SYSREF–
AVDD
DVDD
DVSS
NIC
AVDD
VINA+
VINA–
AVDD
PDWN
CSB
SDIO
SCLK
DNC
SVDD
DVDD
DVSS
NIC
NIC
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TOP VIEW
AD9656
Figure 4. Pin Configuration, Top View
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
AGND,
Exposed Pad
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the device. This exposed pad must be connected to ground for proper operation.
1, 4, 5, 8, 11, 39, 42,
43, 46, 52, 53, 56
AVDD
1.8 V Analog Supply Pins.
2
VIND+
ADC D Analog Input True.
3
VIND−
ADC D Analog Input Complement.
6, 7
CLK−, CLK+
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
9
SYSREF+
Active High JESD204B LVDS SYSREF Input True.
10
SYSREF−
Active High JESD204B LVDS SYSREF Input Complement.
12, 32
DVDD
Digital Supply.
13, 31
DVSS
Digital Ground.
14, 15, 29, 30
NIC
Not Internally Connected. Can be connected to ground if desired.
16
SYNCINB+
Active Low JESD204B LVDS SYNC Input True.
17
SYNCINB−
Active Low JESD204B LVDS SYNC Input Complement.
18, 23, 28
DRVDD
Digital Output Driver Supply.
19
SERDOUT3−
Lane 3 Digital Output Complement.
20
SERDOUT3+
Lane 3 Digital Output True.
21
SERDOUT2+
Lane 2 Digital Output True.
22
SERDOUT2−
Lane 2 Digital Output Complement.
24
SERDOUT1−
Lane 1 Digital Output Complement.
25
SERDOUT1+
Lane 1 Digital Output True.
26
SERDOUT0+
Lane 0 Digital Output True.
27
SERDOUT0−
Lane 0 Digital Output Complement.
33
SVDD
SPI Supply Pin.



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