AD9656

Data Sheet

Rev. A | Page 38 of 46

MEMORY MAP REGISTER TABLE

The AD9656 uses a 3-wire interface and 16-bit addressing. Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1.

When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset, where all of the user registers revert to each default value and Bit 2 is

automatically cleared.

Table 19. Memory Map Registers (SPI Registers/Bits Not Labeled Local Are Global)

Addr

(Hex)

Register Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Notes/

Comments

Chip Configuration Registers

0x00

SPI port

configuration

0

LSB first

Soft reset

1

1

Soft reset

LSB first

0

0x18

0x01

Chip ID

8-bit chip ID[7:0]; AD9656 = 0xC0 (quad, 16-bit, 125 MSPS, JESD204B)

0xC0

Read only.

0x02

Chip grade

Open

Speed grade ID[6:4]; 110 = 125 MSPS

Open

Open

Open

Open

0x62

Read only.

Channel Index and Transfer Registers

0x05

Device index

Open

Open

Open

Open

Data

Channel 3

Data

Channel 2

Data

Channel 1

Data

Channel 0

0x0F

0xFF

Transfer

Open

Open

Open

Open

Open

Open

Open

Initiate

Register

0x100

override

(self

clearing)

0x00

ADC Functions

0x08

Power modes

Open

Open

PDWN

pin

function:

0 = full

power-

down,

1 =

standby

JTX

standby

mode:

0 = ignore

standby,

1 = do not

ignore

standby

Reserved

Power mode:

00 = normal operation,

01 = full power-down,

10 = standby,

11 = digital reset

0x00

0x09

Clock

Open

0

Open

Open

Open

Open

Open

Duty cycle

stabilizer:

0 = off,

1 = on

0x00

0x0A

PLL_STATUS

PLL

locked

status bit:

0 = PLL

is not

locked,

1 = PLL

is locked

Open

Open

Open

Open

Open

Open

JTX link

status:

0 = not

ready,

1 = ready

Read only.

0x0B

Clock divider

Open

Open

Open

Open

Open

Clock divider ratio[2:0]:

000 = divide by 1,

001 = divide by 2,

010 = divide by 3,

011 = divide by 4,

100 = divide by 5,

101 = divide by 6,

110 = divide by 7,

111 = divide by 8

0x00

0x0C

Enhancement

control

Open

Open

Open

Open

Open

Chop mode:

0 = off, 1 = on

Open

Open

0x00

0x0D

Test mode

(local except

for pseudo-

random

number

(PN) sequence

resets)

User input test mode:

00 = single,

01 = alternate,

10 = single once,

11 = alternate once,

(affects user input

test mode only,

Bits[3:0] = 1000)

Reset

PN long

generator

Reset

PN short

generator

Output test mode[3:0] (local):

0000 = off (default),

0001 = midscale short,

0010 = positive full scale (FS),

0011 = negative FS,

0100 = alternating checkerboard,

0101 = PN23 sequence,

0110 = PN9 sequence,

0111 = one/zero word toggle,

1000 = user input,

1001 = 1/0 bit toggle,

1010 = 1× sync,

1011 = one bit high,

1100 = mixed bit frequency

0x00

When set,

the test

data is

placed

on the

output

pins in

place of

normal

data.

0x10

Offset adjust

(local)

8-bit device offset adjustment [7:0] (local); offset adjusts in LSBs from +127 to −128 (twos complement format)

0x00

Device

offset trim.