AD9656EBZ datasheet(44/47 Pages) AD

44 / 47 page

Data Sheet

AD9656

Rev. A | Page 43 of 46

JTX User Pattern (Register 0xA0 to Register 0xA7)

The pattern in these registers is output on all active lanes when

concatenation of Register 0xA0, Register 0xA2, Register 0xA4,

and Register 0xA6 is inserted before the scrambler if Register 0x61,

Bits[5:4] are set to 2. If Register 0x61, Bits[5:4] are set to 1 (a 40-bit

pattern), the concatenation of Register 0xA1, Bits[1:0] and

Resolution/Sample Rate Override (Register 0x100)

This register allows the user to downgrade the resolution and/or

the maximum sample rate (for lower power) in applications that do

not require full resolution and/or sample rate. Settings in this

(Register 0xFF) is written high.

Bits[2:0] do not affect the sample rate; they affect the maximum

sample rate capability of the ADC.

Writing to Register 0x100 reverts other registers to defaults. If

nondefault configurations are desired, write to Register 0x100

first, and then perform other desired SPI operations to preserve

the desired configuration.

User I/O Control 2 (Register 0x101)

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 kΩ pull-down resistor

on the SDIO pin. This setting can limit the loading when many

devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM generator.

This feature is used when applying an external reference.

AD9656EBZ 数据表(PDF) 44 Page - Analog Devices