NET2890 datasheet(20/73 Pages) ETC

20 / 73 page

Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.5.2 Control Write Transfer Details

For control write transfers, the host first sends eight bytes of setup information. The setup bytes are stored

into an 8-byte register bank that can be accessed from the local CPU. After the eight bytes have been stored

into the Setup Registers, the Setup Packet Interrupt status bit is set. If this interrupt is enabled, the local

interrupt IRQ# pin is asserted. The NET2890 will not respond to the host if the Setup Packet Interrupt

status bit is still set from a previous setup packet, and a new setup packet arrives from the host. This

prevents the eight bytes of the previous setup packet from being over-written before the local CPU has read

them.

The local CPU then reads the 8-byte setup packet and prepares to respond to the optional Data transactions.

The number of bytes to be transferred in the Data transactions is specified in the setup packet. When the

setup packet is received, the Control Status Phase Handshake bit is automatically set in anticipation of

the control status phase. While this bit is set, the control status phase will be acknowledged with a NAK,

allowing the local CPU to prepare its handshake response (ACK or STALL). Once the Control Status

Phase Handshake bit cleared, the ACK or STALL handshake will be returned to the host.

During a control write operation, optional Data transactions can follow the Setup transaction. The Data

Out Token Interrupt status bit is set at the beginning of each Data transaction. If this interrupt is enabled,

the local interrupt IRQ# pin is asserted. The bytes corresponding to the Data transaction are stored into the

Endpoint 0 FIFO. If the FIFO fills up and another byte is transferred from the host, the NET2890 will

return a NAK handshake to the host, signaling that the data could not be accepted. After each transaction,

the local CPU should check the USB OUT ACK Sent, USB OUT NAK Sent, and Timeout status bits to

determine if the packet was successfully received.

•

If a packet is not successfully received (NAK or Timeout status) and retries are disabled, the Data

Packet Received Interrupt status bit will be set. The packet data which is in the FIFO or has already

been read by the CPU should be discarded. The host will resend the same packet again.

•

If a packet is not successfully received (NAK or Timeout status) and retries are enabled, the Data

Packet Received Interrupt status bit will not be set, and the data will be automatically flushed from

the FIFO. The host will resend the same packet again. This process is transparent to the local CPU.

•

If the local CPU has stalled this endpoint by setting the Endpoint Stall bit, the NET2890 will not store

any data into the FIFO, and will respond with a STALL acknowledge to the host. There will not be a

Status transaction in this case.

The local CPU can either start polling for valid data immediately after receiving the setup packet, or can

wait for the Data Packet Received Interrupt status bit to be set. As the FIFO is filling up from the USB

side, the local CPU can poll the FIFO status register to determine when a byte is available. Otherwise it can

either poll the Data Packet Received Interrupt status bit, or enable it as an interrupt, and then read the

entire packet from the FIFO at once. If the host tries to write more data than was indicated in the setup

packet, then the local CPU should set the STALL bit for Endpoint 0. In this case there will not be a status

stage from the host.

After all of the optional Data transaction packets have been received, the host will send an IN token,

signifying the Status transaction. The Control Status Interrupt status bit is set after the IN token of the

Status transaction has been received. If this interrupt is enabled, the local interrupt IRQ# pin is asserted.

Until the Control Status Phase Handshake bit is cleared by the local CPU, the NET2890 will respond to

the Status transaction with NAKs, indicating that the device is still processing the setup command. When

the Control Status Phase Handshake bit has been cleared by the local CPU, the NET2890 will respond

with a zero length data packet (transfer OK) or STALL (device had an error).

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