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数据搜索系统，热门电子元器件搜索 |
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NET2890 数据表(PDF) 47 Page - List of Unclassifed Manufacturers |
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NET2890 数据表(HTML) 47 Page - List of Unclassifed Manufacturers |
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47 / 73 page  Specification NET2890 USB Interface Controller ____________________________________________________________________________________ NetChip Technology, Inc., 1999 335 Pioneer Way, Mountain View, California 94041 TEL (650) 526-1490 FAX (650) 526-1494 http://www.netchip.com Rev 2.0, Draft 9, July 16, 1999 47 5.4.9 (Address 1Ah; FIFOCNT) FIFO Count Register (one per Endpoint) Bits Description Read Write Default Value 7:0 FIFO Count. This register returns the number of FIFO entries containing valid data. Values range from 0 (empty) to 128 (full) for Endpoints A through D, and from 0 (empty) to 16 (full) for Endpoint 0. Note: If retries are disabled, and the endpoint is actively involved in a USB packet transfer, the value read from this register may not be valid. Yes No 0 5.4.10 (Address 1Ch;FIFOCTL) FIFO Control Register (one per Endpoint) Bits Description Read Write Default Value 7 Reserved Yes No 0 6 FIFO Valid Mode. This bit is only used for IN endpoints. Setting this bit causes the NET2890 to respond to an IN token with a NAK handshake unless there are more than EPnPKTSIZ bytes in the FIFO or the FIFO Valid bit is set. When this bit is cleared, any data waiting in the endpoint’s FIFO will be sent in response to a n IN token, and the FIFO Valid bit is ignored (except for zero-length packets). Yes Yes 0 5 FIFO Flush. Writing a 1 to this bit causes the FIFO to be flushed and the corresponding FIFO Count register and FIFO Valid bit to be cleared. This bit clears itself, and writing a 0 has no effect. Reading this bit always returns a 0. No Yes 0 4:0 Reserved Yes No 0 5.4.11 (Address 1Eh;FIFOSTAT) FIFO Status Register (one per Endpoint) Bits Description Read Write Default Value 7 FIFO Valid. This bit is only used for IN endpoints. If the FIFO Valid Mode bit is set and there are fewer than EPnPKTSIZ bytes in the FIFO, the NET2890 will respond to IN tokens with NAK handshake unless this bit is set. Setting this bit causes the data in the FIFO to be returned to the host as a short packet. Setting this bit when the FIFO is empty causes a zero-length packet to be returned. This bit is automatically cleared when a short (fewer than EPnPKTSIZ) packet is transmitted to the Host PC. (See EPnPKTSIZ registers). Yes Yes/SET 0 6 Reserved Yes No 0 5 FIFO Overflow. If set, this bit indicates that an attempt was made to write to the FIFO when the FIFO was full. Writing a 1 clears this bit. Yes Yes/CLR 0 4 FIFO Underflow. If set, this bit indicates that an attempt was made to read the FIFO when the FIFO was empty. Writing a 1 clears this bit. Yes Yes/CLR 0 3 FIFO Full. If set, this bit indicates that the FIFO is full. Yes No 0 2 FIFO Empty. If set, this bit indicates that the FIFO is empty. Yes No 1 1:0 Reserved Yes No 0 |
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