NET2890 datasheet(31/73 Pages) ETC

31 / 73 page

Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.8.2 DMA Transfers from NET2890 to Local Bus

A Direct Memory Access (DMA) controller may be used on the local bus to transfer data to and from the

NET2890. For host to device transfers, the local and host CPUs first arrange to transfer a block of data from

host memory to local shared memory. The local CPU then programs the DMA controller for fly-by demand

mode transfers. In this mode, transfers occur only when the NET2890 requests them, and the data is read

from one of the NET2890 endpoint FIFOs and written into local memory during the same bus transaction.

The DMA address counter is programmed to point to the destination memory block in local shared memory,

and the byte count to the number of bytes in the block to be transferred.

After the DMA controller has been programmed, the DMA Request Enable bit is set in the NET2890. The

USB host performs OUT data transactions over the USB bus to an endpoint’s FIFO in the NET2890.

As long as there is data available in the selected endpoint’s FIFO, the NET2890 will request local DMA

transfers by asserting DRQ. The DMA controller then requests the local bus from the local CPU. After the

DMA controller has been granted the bus, it drives a valid memory address and asserts DACK#, IOR#, and

MEMW#, thus transferring a byte from an endpoint’s FIFO to local memory. The DMA transfers continue

until the DMA byte count reaches zero. If the EOT# pin is asserted during the last DMA transfer, the EOT

Interrupt status bit will be set. If this interrupt is enabled, the local interrupt IRQ# pin is asserted.

4.8.3 DMA Transfers from Local Bus to NET2890

For device to host transfers, the local and host CPUs first arrange to transfer a block of data from local

memory to host memory. The local CPU then programs the DMA controller for fly-by demand mode

transfers. In this mode, transfers occur only when the NET2890 requests them, and the data is read from

local memory and written into the selected endpoint’s FIFO during the same bus transaction. The DMA

address counter is programmed to point to the source memory block in local memory, and the byte count to

the number of bytes in the block to be transferred. After the DMA controller has been programmed, the

DMA Request Enable bit is set in the NET2890. As long as there is space available in the selected

endpoint’s FIFO, and the byte count is non-zero, the NET2890 will request DMA transfers by asserting

DRQ. The DMA controller then requests the local bus from the local CPU. After the DMA controller has

been granted the bus, it drives a valid memory address and asserts DACK#, MEMR#, and IOW#, thus

transferring a byte from memory to the endpoint’s FIFO.

The USB host sends an IN token to the NET2890 and starts an IN data transaction from the selected

endpoint’s FIFO. The DMA transfers continue until the DMA byte count reaches zero. If the EOT# pin is

asserted during the last DMA transfer, the EOT Interrupt status bit will be set. If this interrupt is enabled,

the local interrupt IRQ# pin is asserted.

A single DMA setup can be used to transfer multiple packets. The DMA Request signal (DRQ) is asserted

anytime there is space available in the FIFO. The endpoint’s maximum packet size registers control the

maximum number of bytes transmitted to the host in the packet.

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