NET2890 datasheet(4/73 Pages) ETC

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Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.9.3

Device-Remote Wake-Up ......................................................................................................33

4.9.4

Resume Interrupt................................................................................................................... 33

4.10

ROOT PORT RESET......................................................................................................................... 34

4.11

NET2890 POWER CONFIGURATION ............................................................................................... 34

4.11.1

Bus-Powered Device ............................................................................................................. 34

4.11.2

Self-Powered Device ............................................................................................................. 34

4.11.3

Low-Power Modes ................................................................................................................ 35

CONFIGURATION REGISTERS .................................................................................................... 36

5.1

REGISTER DESCRIPTION ................................................................................................................. 36

5.2

REGISTER SUMMARY ..................................................................................................................... 36

5.2.1

Base registers (unpaged)....................................................................................................... 36

5.2.2

Endpoint / FIFO registers (paged) ....................................................................................... 37

5.2.3

Setup Packet registers (paged).............................................................................................. 37

5.2.4

Indexed registers ................................................................................................................... 38

5.3

BASE REGISTERS............................................................................................................................ 39

5.3.1

(Address 00h; PAGESEL) Paged Register Select ................................................................. 39

5.3.2

(Address 01h; MAINCTL) Main Control Register ................................................................ 39

5.3.3

(Address 02h; DMACTL) DMA Control Register ................................................................. 39

5.3.4

(Address 03h; IRQSTAT1) Interrupt Status Register 1 ......................................................... 40

5.3.5

(Address 04h; IRQSTAT2) Interrupt Status Register 2 ......................................................... 40

5.3.6

(Address 06h; IDXADDR) Index Register Address............................................................... 41

5.3.7

(Address 07h; IDXDATA) Indexed Register Data ................................................................ 41

5.3.8

(Address 0Bh; PKTLENLSB) Packet Length (LSB) .............................................................. 41

5.3.9

(Address 0Ch; PKTLENMSB) Packet Length (MSB)............................................................ 41

5.4

ENDPOINT / FIFO REGISTERS ........................................................................................................ 42

5.4.1

(Address 10h; EPCFG) Endpoint Configuration Register (one per Endpoint) .................... 42

5.4.2

(Address 11h; EPRSPSET) Endpoint Response Set Register (one per Endpoint) ................ 43

5.4.3

(Address 12h; EPRSPCLR) Endpoint Response Clear Register (one per Endpoint)............ 44

5.4.4

(Address 13h; EPIRQENB) Endpoint Interrupt Enable Register (one per Endpoint) .......... 45

5.4.5

(Address 14h; EPIRQSTAT) Endpoint Interrupt Status Register (one per Endpoint) .......... 45

5.4.6

(Address 15h; EPUSBSTAT) Endpoint USB Status Register (one per Endpoint)................. 46

5.4.7

(Address 16h; EPDOUT) Endpoint Data Out Register (one per Endpoint) ......................... 46

5.4.8

(Address 17h; EPDIN) Endpoint Data In Register (one per Endpoint)................................ 46

5.4.9

(Address 1Ah; FIFOCNT) FIFO Count Register (one per Endpoint)................................... 47

5.4.10

(Address 1Ch;FIFOCTL) FIFO Control Register (one per Endpoint) ................................. 47

5.4.11

(Address 1Eh;FIFOSTAT) FIFO Status Register (one per Endpoint) .................................. 47

5.5

SETUP REGISTERS .......................................................................................................................... 48

5.5.1

(Address 10h; SETUP0) Setup Byte 0 ................................................................................... 48

5.5.2

(Address 11h; SETUP1) Setup Byte 1 ................................................................................... 48

5.5.3

(Address 12h; SETUP2) Setup Byte 2 ................................................................................... 48

5.5.4

(Address 13h; SETUP3) Setup Byte 3 ................................................................................... 48

5.5.5

(Address 14h; SETUP4) Setup Byte 4 ................................................................................... 49

5.5.6

(Address 15h; SETUP5) Setup Byte 5 ................................................................................... 49

5.5.7

(Address 16h; SETUP6) Setup Byte 6 ................................................................................... 49

5.5.8

(Address 17h; SETUP7) Setup Byte 7 ................................................................................... 49

5.6

INDEXED REGISTERS...................................................................................................................... 50

5.6.1

(Index 00h; LOCALCTL) Local Bus Control ........................................................................ 50

5.6.2

(Index 01h; OURADDR) Our USB Address Register ........................................................... 50

5.6.3

(Index 02h; IRQENB1) Interrupt Enable Register 1............................................................. 50

5.6.4

(Index 03h; IRQENB2) Interrupt Enable Register 2............................................................. 51

5.6.5

(Index 07h; FRAMELSB) Frame Counter (LSB) .................................................................. 51

5.6.6

(Index 08h; FRAMEMSB) Frame Counter (MSB) ................................................................ 51

5.6.7

(Index 0Ch; DIAG) Diagnostic Register ............................................................................... 52

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