NET2890 datasheet(32/73 Pages) ETC

32 / 73 page

Specification

NET2890 USB Interface Controller

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NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.8.4 Terminating DMA Transfers

The EOT# signal is used to halt a DMA transfer, and is typically provided by an external DMA controller.

It should be asserted while DACK# and IOR# or IOW# are simultaneously active to indicate that DMA

activity has stopped. Although an EOT# signal indicates that DMA has terminated, the USB transfer is not

complete until the last byte has been transferred from the endpoint’s FIFO to the USB. The EOT# input

resets the NET2890 DMA Request Enable bit.

When EOT# is detected, the FIFO VALID bit is

automatically set, causing the remaining data to be sent to the host. If there is no data in the FIFO, then a

zero length packet will be returned in response to the next IN token.

If no EOT# signal is provided by the DMA controller, the local CPU can terminate the DMA transfer at any

time by resetting the NET2890 DMA Request Enable bit. If the NET2890 DMA Request Enable bit is

cleared during the middle of a DMA cycle, the current cycle will complete before DMA requests are

terminated. The FIFO Valid (FIFOSTAT[7]) bit is not automatically set when the DMA Request Enable

(DMACTL[3]) is cleared. In this case, the CPU needs to explicitly set this bit if there is a short packet in

the FIFO.

If a packet has an odd number of bytes, it is not allowable to pad the packet with one extra byte. If a DMA

controller can only transfer an even number of bytes, then the local CPU can be used to write the last odd

byte into the FIFO. This approach works as long as the DMA EOT# pin is not used. If the EOT# pin is

asserted at the end of a DMA, the FIFO Valid (FIFOSTAT[7]) bit is automatically set. This could be a

problem since the last odd byte has not been written to the FIFO by the local CPU. There are no other

limitations to intermixing CPU and DMA transfers, as long as DACK# is not asserted during CPU transfers.

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