NET2890 datasheet(30/73 Pages) ETC

30 / 73 page

Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.8 Local Bus

Data passes between the local bus and the USB through the appropriate endpoint’s FIFO. The local bus is

an 8-bit non-multiplexed bus, and is controlled with a simple set of interface signals. The NET2890 acts

only as a slave on the local bus. When the NET2890 is acting as a local bus slave, a CPU on the local bus

can access all of the internal configuration registers, as well as the FIFOs.

4.8.1 Maximum Throughput

Note that maximum USB throughput is 1.5 Mbytes/sec, so the local bus utilization for accessing the

NET2890 is very low. This allows a fast local CPU to perform many other operations during USB data

transfers.

4.8.1.1 CPU writes to FIFO

•

T1 (address setup) : 5

•

T3 (write strobe width) : 5

•

T7 (I/O recovery) : 64

•

Total = 74 ns

13.5 Mbytes/sec

•

If the address setup can be overlapped with the I/O recovery, then

Total = 69 ns

14.5 Mbytes/sec

4.8.1.2 CPU reads from FIFO

•

T1 (address setup) : 5

•

T4 (read access time) : 28

•

Target setup time: (assume 5 ns)

•

T7 (I/O recovery) : 42

•

Total = 80 ns

12.5 Mbytes/sec

•

If the address setup can be overlapped with the I/O recovery, then

Total = 75 ns

13.3 Mbytes/sec

4.8.1.3 DMA writes to FIFO

•

The maximum rate of DMA write transfers is determined by how quickly DACK# and IOW# are

asserted after DRQ. An internal state machine asserts DRQ on the rising edge of a 48MHz clock.

With a clock period of 20.8ns, a clock to output delay of 5ns on DRQ, and a 5ns setup time on

DACK# and IOW#, both DACK# and IOW# would have to be asserted within 10.8ns of DRQ in

order to be sampled on the next rising edge of the clock. Then DACK# and IOW# would both

need to be negated 25 nsec later to minimize the length of the cycle. If this could be accomplished,

the minimum cycle time would be 125ns yielding a burst rate of 8 Mbytes/sec.

4.8.1.4 DMA reads from FIFO

•

The maximum rate of DMA read transfers is the same as the maximum rate of DMA write

transfers.

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