NET2890 datasheet(21/73 Pages) ETC

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Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

4.5.2.1 Control Read Transfer

A successful control read transfer from Control Endpoint 0 consists of the following:

Transaction

Stage

Packet Contents

# of

bytes

Source

Setup

Setup Token

SETUP PID, address, endpoint, and CRC5

Host

Data

DATA0 PID, 8 data bytes, and CRC16

Host

Status

ACK

NET2890

Data (zero, one, or

more packets)

IN Token

IN PID, address, endpoint, and CRC5

Host

Data (1/0)

DATA PID, N data bytes, and CRC16

N+3

NET2890

Status

ACK

Host

Status

OUT Token

OUT PID, address, endpoint, and CRC5

Host

Data

DATA1 PID, zero length packet, and CRC5

Host

Status

ACK

NET2890

The Setup transaction is processed in the same way as for control write transfers.

During the Data transaction, zero, one or more data packets are read from the Endpoint 0 FIFO. For each

packet:

•

Interrupt status bits are set and can interrupt the local CPU

•

The local CPU writes data to the FIFO

•

If there is no data in the FIFO, a NAK or zero length packet is returned to the host

•

The Host returns an ACK to the NET2890 if no error has occurred.

For a successful Status transaction, the Host sends a zero length data packet, and the NET2890 responds

with an ACK. A NAK or STALL can be returned if an error occurred.

4.5.2.2 Control Read Transfer Details

For control read transfers, the host first sends eight bytes of setup information. The setup bytes are stored

into an 8-byte register bank that can be accessed from the local CPU. After the eight bytes have been stored

into the Setup Registers, the Setup Packet Interrupt status bit is set. If this interrupt is enabled, the local

interrupt IRQ# pin is asserted. The NET2890 will not respond to the host if the Setup Packet Interrupt

status bit is still set from a previous setup packet, and a new setup packet arrives from the host. This

prevents the eight bytes of the previous setup packet from being over-written before the local CPU has read

them.

The local CPU then reads the 8-byte setup packet and prepares to respond to the optional Data transactions.

The number of bytes to be transferred in the Data transactions is specified in the setup packet. When the

setup packet is received, the Control Status Phase Handshake bit is automatically set. While this bit is

set, the control status phase will be acknowledged with a NAK, allowing the local CPU to prepare its

handshake response (ACK or STALL). Once the Control Status Phase Handshake bit is cleared, the

ACK or STALL handshake will be returned to the host.

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