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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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NET2890 数据表(PDF) 39 Page - List of Unclassifed Manufacturers |
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NET2890 数据表(HTML) 39 Page - List of Unclassifed Manufacturers |
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39 / 73 page  Specification NET2890 USB Interface Controller ____________________________________________________________________________________ NetChip Technology, Inc., 1999 335 Pioneer Way, Mountain View, California 94041 TEL (650) 526-1490 FAX (650) 526-1494 http://www.netchip.com Rev 2.0, Draft 9, July 16, 1999 39 5.3 Base Registers 5.3.1 (Address 00h; PAGESEL) Paged Register Select Bits Description Read Write Default Value 7:5 Paged Register Set select. These bits select one of the paged sets of configuration registers. The select value pages one of the sets of registers into the address range 10-1F. All values not listed below are Reserved. Value Paged Register Set 0h Endpoint 0 (Control) 1h Endpoint A 2h Endpoint B 3h Endpoint C 4h Endpoint D 7h Setup Packet Registers Yes Yes 0 4:0 Reserved Yes No 0 5.3.2 (Address 01h; MAINCTL) Main Control Register Bits Description Read Write Default Value 7:5 Reserved Yes No 0 4 Retry Enable. If set, this bit enables the automatic retry feature. If an error occurs during an IN packet, the same packet data is transmitted when the next IN token is received. If an error occurs during an OUT packet, the corresponding FIFO is flushed. No interrupts or status bits will change as a result of failed packets. Note that isochronous endpoints are never retried. Yes Yes 1 3 Device Remote Wake-up Enable. If set, this bit enables the WAKEUP# pin to cause a device remote wake-up. Yes Yes 0 2 Device Configured. When the NET2890 has been successfully configured by the host, the local CPU can set this bit which causes the DEVCFG# output pin to be asserted. This bit is cleared when a root port reset is detected. Yes Yes 0 1 Power Good. When the PWRGOOD# pin is asserted, this bit is read as a one, indicating that the local power supply is operational. Yes No 0 0 Self Powered. When the BUSPWR# pin is negated (high), this bit is read as a one, indicating that the NET2890 is operating in the self powered mode. Yes No 0 5.3.3 (Address 02h; DMACTL) DMA Control Register Bits Description Read Write Default Value 7:5 Reserved Yes No 0 4 DMA Request. This status bit reflects the state of the DRQ output pin, and allows a CPU on the local bus to monitor DMA transfers. Yes No 0 3 DMA Request Enable. Writing a 1 to this bit causes the NET2890 to start requesting DMA cycles from a DMA controller on the local bus. If the EOT# input is asserted, this bit is automatically reset. A CPU on the local bus may also explicitly reset this bit to terminate a DMA transfer. If the CPU sets the FIFO Valid bit of the endpoint selected by field 2:0, this bit is cleared. This bit can be read to determine whether a DMA transfer is still in progress. Yes Yes 0 2:0 DMA Endpoint Select. This field determines which Endpoint is being accessed during a DMA transfer. 000 = Endpoint 0, 001 = A, 010 = B, 011 = C, 100 = D. Yes Yes 0 |
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