NET2890 datasheet(44/73 Pages) ETC

44 / 73 page

Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

5.4.3 (Address 12h; EPRSPCLR) Endpoint Response Clear Register (one per

Endpoint)

Note: Writing a 1 to a bit position clears that bit and writing a 0 has no effect.

Bits

Description

Read

Write

Default

Value

Reserved.

Yes

End of Transfer Response. This bit is only used for IN endpoints. If FIFO Valid

Mode is false, setting this bit causes the endpoint to automatically terminate USB

transfers with a zero length packet when necessary. If the last packet sent was full

(Short Packet Transferred is false), and an IN token arrives when the FIFO is empty,

the endpoint returns a zero length packet (instead of NAK) to indicate end of transfer

to the host.

Yes

Yes/Clr

Interrupt Mode.

This bit is only used for INTERRUPT endpoints. For normal interrupt data, this bit

should be set to zero and standard data toggle protocol is followed. When this

interrupt endpoint is used for isochronous rate feedback information, this bit should

be set high. In this mode the data toggle bit is changed after each packet is sent to the

host without regard to handshaking. No packet retries are performed in the rate

feedback mode.

Yes

Yes/Clr

Control Status Phase Handshake. This bit is only used for endpoint 0. This bit is

automatically set when a setup packet is detected. While the bit is set, a control status

phase will be acknowledged with a NAK. Once cleared, the proper response will be

returned to the host (ACK for Control Reads and zero-length packets for Control

Writes).

Yes

Yes/Clr

Receive Handshake Mode. This bit is only used for OUT endpoints. This bit selects

the response if the previous receive packet has not been processed by the local CPU.

If this bit is low, the NET2890 will accept the OUT packet if there is space available

in the endpoint’s FIFO. If this bit is high, the NET2890 will respond to the host with

a NAK if an OUT packet is received and the Data Packet Received Interrupt status

bit is still set from the previous packet.

Yes

Yes/Clr

Reserved.

Yes

Endpoint Toggle. This bit is used to clear the endpoint data toggle bit. When an

Endpoint Clear Feature Standard Request to clear a stall bit is detected by the local

CPU, it must write a 1 to this bit, thus resetting the toggle. Reading this bit returns

the current state of the endpoint data toggle bit.

Yes

Yes/Clr

Endpoint Stall. This bit is used to clear the endpoint stall bit. When an Endpoint

Clear Feature Standard Request to the stall bit is detected by the local CPU, it must

write a 1 to this bit. Reading this bit returns the current state of the endpoint stall bit.

Yes

Yes/Clr

NET2890 数据表(PDF) 44 Page - List of Unclassifed Manufacturers

NET2890 数据表(HTML) 44 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载

链接网址

NET2890 数据表(PDF) 44 Page - List of Unclassifed Manufacturers

NET2890 数据表(HTML) 44 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表 下载

链接网址

数据表下载