NET2890 datasheet(22/73 Pages) ETC

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Specification

NET2890 USB Interface Controller

____________________________________________________________________________________

NetChip Technology, Inc., 1999

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 2.0, Draft 9, July 16, 1999

During a control read operation, optional Data transactions can follow the Setup transaction. After the Setup

transaction, the local CPU can start writing the first byte of packet data into the Endpoint 0 FIFO in

anticipation of the Data transaction. The Data In Token Interrupt status bit is set at the beginning of each

Data transaction. If this interrupt is enabled, the local interrupt IRQ# pin is asserted. If there is data in the

Endpoint 0 FIFO, it is returned to the host. If Endpoint 0 has no data to return, it returns either a zero

length packet (signaling that there is no more data available) or a NAK handshake (the data is not available

yet), depending on the FIFO Valid and FIFO Valid Mode bits.

FIFO

Valid

Mode

FIFO

Valid

Bit

End of

Transfer

Response Bit

Size of

Packet

Amount of Data in

FIFO

Action

empty

NAK to host

Maximum

empty

Zero length packet to host

< Maximum

empty

NAK to host

empty

Zero length packet to host

Return data to host

< Max Packet Length

NAK to host

>= Max Packet Length

Return data to host

empty

Zero length packet to host

Return data to host

After each packet has been sent to the host, the Data Packet Transmitted Interrupt status bit is set. If this

interrupt is enabled, the local interrupt IRQ# pin is asserted. If retries are disabled, the local CPU should

check the USB IN ACK Sent, USB IN NAK Sent, and Timeout status bits to determine if the packet was

successfully transmitted.

•

If a packet is not successfully transmitted (Timeout status bit set) and retries are enabled, the Data

Packet Transmitted Interrupt status bit will not be set, and the same packet is sent to the host when

another IN token is received. The retry operation is transparent to the local CPU.

•

If a packet is not successfully transmitted (Timeout status bit set) and retries are disabled, the Data

Packet Transmitted Interrupt status bit will be set. The local CPU needs to flush the FIFO and

reload the packet for the next IN token.

•

If the host tries to read more data than was requested in the setup packet, the local CPU should set the

STALL bit for the endpoint.

After all of the optional Data transaction packets have been transmitted, the host will send an OUT token,

followed by a zero length data packet, signifying the Status transaction. The Control Status Interrupt

status bit is set after the OUT token of the Status transaction has been received. If this interrupt is enabled,

the local interrupt IRQ# pin is asserted. Until the Control Status Phase Handshake bit is cleared by the

local CPU, the NET2890 will respond to the Status transaction with NAKs, indicating that the device is still

processing the command specified by the Setup transaction. When the Control Status Phase Handshake

bit has been cleared by the local CPU, the NET2890 will respond with an ACK (transfer OK) or STALL

(Endpoint 0 is stalled).

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NET2890 数据表(PDF) 22 Page - List of Unclassifed Manufacturers

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