数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

NET2890 数据表(PDF) 67 Page - List of Unclassifed Manufacturers

部件名 NET2890
功能描述  USB Interface Controller
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

NET2890 数据表(HTML) 67 Page - List of Unclassifed Manufacturers

Back Button NET2890 Datasheet HTML 63Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 64Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 65Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 66Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 67Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 68Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 69Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 70Page - List of Unclassifed Manufacturers NET2890 Datasheet HTML 71Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 67 / 73 page
background image
Specification
NET2890 USB Interface Controller
____________________________________________________________________________________
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 2.0, Draft 9, July 16, 1999
67
7.4.2 USB Port AC/DC Specification Notes
1.
All voltages measured from the local ground potential, unless otherwise specified.
2.
All timings use a capacitive load (CL) to ground of 50 pF, unless otherwise specified.
3.
Full Speed timings have a 1.5 k
Ω pull-up to 3.3 V on the D+ data line.
4.
Measured from 10% to 90% of the data signal.
5.
The rising and falling edges should be smoothly transitioning (monotonic).
6.
Timing difference between the differential data signals.
7.
Measured at crossover point of differential data signals.
8.
The maximum load specification is the maximum effective capacitive load allowed that meets the target
hub VBUS droop of 330 mV.
9.
VDDC and IDDC refer to core power supply (pins designated VDD). VDDL and IDDL refer to local bus power
supply (pins designated VDDL(LOCAL)).
7.4.3 USB Port AC Waveforms
Differential
Data Lines
90%
10%
90%
10%
Rise Time
Fall Time
t
R
t
F
C
L
C
L
Full Speed: 4 to 20ns at C
L = 50pF
Figure 7-1. Data Signal Rise and Fall Time



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com