AD9957SLASHPCBZ datasheet(25/61 Pages) AD

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Data Sheet

AD9957

Rev. F | Page 25 of 61

QUADRATURE MODULATOR

The digital quadrature modulator stage shifts the frequency of

the baseband spectrum of the incoming data stream up to the

desired carrier frequency (a process known as upconversion).

At this point, the baseband data, which was delivered to the

device at an I/Q sample rate of fIQ, has been upsampled to a rate

equal to the frequency of SYSCLK, making the data sampling

rate equal to the sampling rate of the carrier signal.

A direct digital synthesizer (DDS) controls the frequency of the

carrier signal. The DDS very precisely generates the desired

carrier frequency from the internal reference clock (SYSCLK).

The carrier is applied to the I and Q multipliers in quadrature

fashion (90° phase offset) and summed, yielding a data stream

that represents the quadrature modulated carrier.

The modulation is performed digitally, avoiding the phase

offset, gain imbalance, and crosstalk issues commonly associated

with analog modulators. Note that the modulated, so-called

signal is a number stream sampled at the rate of SYSCLK, the

same rate at which the DAC is clocked.

A spectral invert bit controls the orientation of the modulated

signal with respect to the carrier. This bit resides in each of the

eight profile registers. By default, the time domain output of the

quadrature modulator takes the form

I(t) × cos(ωt) − Q(t) × sin(ωt)

(2)

When the spectral invert bit is asserted, it becomes

I(t) × cos(ωt) + Q(t) × sin(ωt)

(3)

DDS CORE

The direct digital synthesizer (DDS) block generates sine

and/or cosine signals. In single tone mode, the DDS generates

either a digital sine or cosine waveform based on the select DDS

sine output bit. In QDUC mode, the DDS generates the quadra-

ture carrier reference signal that digitally modulates the I/Q

baseband signal.

The DDS output frequency is tuned using registers accessed via

the serial I/O port. This allows for both precise tuning and

instantaneous changing of the carrier frequency.

The equation relating output frequency (fOUT) of the DDS to the

frequency tuning word (FTW) and the system clock (fSYSCLK) is

SYSCLK

OUT

FTW













(4)

where FTW is a decimal number from 0 to 2,147,483,647 (231 − 1).

Solving for FTW yields

























SYSCLK

OUT

round

FTW

(5)

where the round() function means to round the result to the

nearest integer. For example, for fOUT = 41 MHz and fSYSCLK =

122.88 MHz, then FTW = 1,433,053,867 (0x556AAAAB).

In single tone mode, the DDS frequency, phase, and amplitude

are all programmable via the serial I/O port. The amplitude

is controlled by means of a digital multiplier using a 14-bit

fractional scale value called the amplitude scale factor (ASF).

The LSB weight is 2−14, yielding a multiplier range of 0 to

0.99993896484375 (1 − 2−14). To bypass the ASF multiplier,

program the appropriate control register bit (see the details of

CFR2, Bit 24 in the Register Bit Descriptions section). When

bypassed, the ASF multiplier clocks are disabled to conserve

power. The phase offset is controlled by means of a digital adder

that uses a 14-bit offset value called the phase offset word (POW).

The adder is situated between the phase accumulator and the

angle-to-amplitude conversion logic in the DDS core. The adder

applies the POW to the instantaneous phase values produced by

the DDS phase accumulator. The adder is MSB aligned with the

phase accumulator yielding an LSB weight of 2−14 (which equates to

a resolution of ~0.022° or ~0.000383 radians). Both the ASF and

the POW are available for each of the eight profiles.

INVERSE SINC FILTER

The sampled carrier data stream is the input to the digital-to-

analog converter. The DAC output spectrum is shaped by the

characteristic sin(x)/x (or sinc) envelope, due to the intrinsic

zero-order hold effect associated with DAC-generated signals.

The shape of the sinc envelope is well known and can be

compensated for. The inverse sinc filter preceding the DAC

provides this compensation.

The inverse sinc filter is implemented as a digital FIR filter. Its

response characteristic very nearly matches the inverse of the

sinc envelope, as shown in Figure 37 (along with the sinc

envelope for comparison).

The inverse sinc filter is enabled through a bit in the register

map. The filter tap coefficients are listed in Table 4. The filter

predistorts the data prior to its arrival at the DAC to compensate

for the sinc envelope that otherwise distorts the spectrum.

When the inverse sinc filter is enabled, it introduces a ~3.0 dB

insertion loss. The inverse sinc compensation is effective for

output frequencies up to 40% (nominally) of the DAC sample rate.

Table 4. Inverse Sinc Filter Tap Coefficients

Tap No.

Tap Value

Tap No.

−35

+134

−562

+6729

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