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AD9957/PCBZ 数据表(PDF) 3 Page - Analog Devices |
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AD9957/PCBZ 数据表(HTML) 3 Page - Analog Devices |
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3 / 61 page ![]() Data Sheet AD9957 Rev. F | Page 3 of 61 Sync Generator ............................................................................41 Sync Receiver ...............................................................................41 Setup/Hold Validation ................................................................42 Synchronization Example ..........................................................44 I/Q Path Latency .........................................................................45 Example ....................................................................................45 Power Supply Partitioning .............................................................46 3.3 V Supplies ..............................................................................46 DVDD_I/O (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56, Pin 66) ......................................................................................46 AVDD (Pin 74 to Pin 77 and Pin 83) ...................................46 1.8 V Supplies ..............................................................................46 DVDD (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, Pin 64) .....46 AVDD (Pin 3)..........................................................................46 AVDD (Pin 6) ..........................................................................46 AVDD (Pin 89 and Pin 92) ....................................................46 Serial Programming ........................................................................47 Control Interface—Serial I/O....................................................47 General Serial I/O Operation ....................................................47 Instruction Byte...........................................................................47 Instruction Byte Information Bit Map .................................47 Serial I/O Port Pin Descriptions ...............................................47 SCLK—Serial Clock................................................................47 CS—Chip Select Bar ...............................................................47 SDIO—Serial Data Input/Output .........................................47 SDO—Serial Data Out ...........................................................48 I/O_RESET—Input/Output Reset ........................................48 I/O_UPDATE—Input/Output Update ................................48 Serial I/O Timing Diagrams ......................................................48 MSB/LSB Transfers .....................................................................48 I/O_UPDATE, SYNC_CLK, and System Clock Relationships .......................................................................................................49 Register Map and Bit Descriptions ...............................................50 Register Map................................................................................50 Register Bit Descriptions............................................................55 Control Function Register 1 (CFR1)....................................55 Control Function Register 2 (CFR2)....................................56 Control Function Register 3 (CFR3)....................................58 Auxiliary DAC Control Register...........................................58 I/O Update Rate Register.......................................................58 RAM Segment Register 0.......................................................58 RAM Segment Register 1.......................................................59 Amplitude Scale Factor (ASF) Register ...............................59 Multichip Sync Register .........................................................59 Profile Registers...........................................................................60 Profile[7:0] Register—Single Tone .......................................60 Profile[7:0] Register—QDUC ...............................................60 RAM Register ..........................................................................60 GPIO Configuration Register ...............................................60 GPIO Data Register ................................................................60 Outline Dimensions........................................................................61 Ordering Guide ...........................................................................61 |
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