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Data Sheet

AD9957

Rev. F | Page 39 of 61

POWER-DOWN CONTROL

The AD9957 offers the ability to independently power down four

specific sections of the device. Power-down functionality applies

to the digital core, DAC, auxiliary DAC, and REFCLK input.

A power-down of the digital core disables the ability to update

the serial I/O port. However, the digital power-down bit can

still be cleared via the serial port to prevent the possibility of a

nonrecoverable state.

Software power-down is controlled through four independent

power-down bits in CFR1. Software control requires forcing the

EXT_PWR_DWN pin to a Logic 0 state. In this case, setting the

desired power-down bits (via the serial I/O port) powers down

the associated functional block; clearing the bits restores the

function.

Alternatively, all four functions can be simultaneously powered

down via external hardware control through the EXT_PWR_DWN

pin. Forcing this pin to Logic 1 powers down all four circuit

blocks, regardless of the state of the power-down bits. That is,

the independent power-down bits in CFR1 are ignored and

overridden when EXT_PWR_DWN is Logic 1.

Based on the state of the external power-down control bit, the

EXT_PWR_DWN pin produces either a full power-down or a

fast recovery power-down. The fast recovery power-down mode

maintains power to the DAC bias circuitry and the PLL, VCO,

and input section of the REFCLK circuitry. Although the fast

recovery power-down does not conserve as much power as the

full power-down, it allows the device to very quickly awaken

from the power-down state.

GENERAL-PURPOSE I/O (GPIO) PORT

The GPIO function is only available when the AD9957 is

programmed for QDUC mode and the Blackfin interface mode

is active. Because the Blackfin serial interface uses only two of

the 18 parallel data port pins (D[5:4]), the remaining 16 pins

(D[17:6] and D[3:0]) are available as a GPIO port.

Each of these 16 pins is assigned a unique bit in both the 16-bit

GPIO configuration register and the 16-bit GPIO data register.

The status of each bit in the GPIO configuration register assigns

the associated pin as either a GPIO input or output (0 = input,

1 = output) based on the data listed in Table 11.

When a GPIO pin is programmed as an output, the logic state

written to the associated bit of the GPIO data register (via the

serial I/O port) appears at the GPIO pin. When a GPIO pin is

programmed as an input, the logic state of the GPIO pin can be

read (via the serial I/O port) in the associated bit position in the

GPIO data register. Note that the GPIO data register does not

require an I/O update.

Table 11. GPIO Pins vs. Configuration and Data Register Bits

Pin Mnemonic

Configuration Bit

Data Bit

D17

D16

D15

D14

D13

D12

D11

D10

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