AD9957SLASHPCBZ datasheet(56/61 Pages) AD

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AD9957

Data Sheet

Rev. F | Page 56 of 61

Bit (s)

Mnemonic

Description

OSK (Output Shift

Keying) Enable

0: OSK disabled (default).

1: OSK enabled.

Select Auto-OSK

Ineffective unless CFR1, Bit 9 = 1.

0: manual OSK enabled (default).

1: automatic OSK enabled.

Digital Power-

Down

This bit is effective without the need for an I/O update.

0: clock signals to the digital core are active (default).

1: clock signals to the digital core are disabled.

DAC Power-Down

0: DAC clock signals and bias circuits are active (default).

1: DAC clock signals and bias circuits are disabled.

REFCLK Input

Power-Down

This bit is effective without the need for an I/O update.

0: REFCLK input circuits and PLL are active (default).

1: REFCLK input circuits and PLL are disabled.

Auxiliary DAC

Power-Down

0: auxiliary DAC clock signals and bias circuits are active (default).

1: auxiliary DAC clock signals and bias circuits are disabled.

External Power-

Down Control

0: assertion of the EXT_PWR_DWN pin affects full power-down (default).

1: assertion of the EXT_PWR_DWN pin affects fast recovery power-down.

Auto Power-Down

Enable

Ineffective when CFR1[25:24] = 01b.

0: disable power-down (default).

1: when the TxENABLE pin is Logic 0, the baseband signal processing chain is flushed of residual data and the

clocks are automatically stopped. Clocks restart when the TxENABLE pin is a Logic 1.

SDIO Input Only

0: configures the SDIO pin for bidirectional operation; 2-wire serial programming mode (default).

1: configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial programming mode.

LSB First

0: configures the serial I/O port for MSB first format (default).

1: configures the serial I/O port for LSB first format.

Control Function Register 2 (CFR2)

Address 0x01, four bytes are assigned to this register.

Table 19. Bit Descriptions for CFR2 Register

Bit (s)

Mnemonic

Description

Blackfin Interface Mode Active

Valid only when CFR1[25:24] = 00b (quadrature modulation mode).

0: Pin D[17:0] configured as an 18-bit parallel port (default).

1: Pin D[5:4] configured as a dual serial port compatible with the Blackfin serial interface.

Pin D[17:6] and Pin D[3:0] become available as a 16-bit GPIO port.

Blackfin Bit Order

Valid only when CFR2, Bit 31 = 1.

0: the dual serial port (BFI) configured for MSB first operation (default).

1: the dual serial port (BFI) configured for LSB first operation.

Blackfin Early Frame Sync Enable

Valid only when CFR2, Bit 31 = 1.

0: the dual serial port (BFI) configured to be compatible with Blackfin late frame sync

operation (default).

1: the dual serial port (BFI) configured to be compatible with Blackfin early frame sync

operation.

[28:25]

Open

Enable Profile Registers as ASF Source

Valid only when CFR1[25:24] = 01b (single tone mode) and CFR1, Bit 9 = 0 (OSK disabled).

0: amplitude scale factor bypassed (unity gain).

1: the active profile register determines the amplitude scale factor.

Internal I/O Update Active

This bit is effective without the need for an I/O update.

0: serial I/O programming is synchronized with external assertion of the I/O_UPDATE pin,

which is configured as an input pin (default).

1: serial I/O programming is synchronized with an internally generated I/O update signal

(the internally generated signal appears at the I/O_UPDATE pin, which is configured as

an output pin).

AD9957/PCBZ 数据表(PDF) 56 Page - Analog Devices

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AD9957/PCBZ 数据表(PDF) 56 Page - Analog Devices

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