AD9957SLASHPCBZ datasheet(37/61 Pages) AD

37 / 61 page

Data Sheet

AD9957

Rev. F | Page 37 of 61

ADDITIONAL FEATURES

OUTPUT SHIFT KEYING (OSK)

The OSK function (Figure 53) is only available in single tone

mode. It allows the user to control the output signal amplitude

of the DDS. Both manual and automatic modes are available.

OSK ENABLE

AMPLITUDE SCALE FACTOR

(ASF[15:2])

AMPLITUDE RAMP RATE

(ASF[31:16])

AMPLITUDE STEP SIZE

(ASF[1:0])

MANUAL OSK EXTERNAL

AUTO OSK ENABLE

OSK

DDS CLOCK

TO DDS

AMPLITUDE

CONTROL

PARAMETER

LOAD ARR AT I/O_UPDATE

OSK

CONTROLLER

Figure 53. OSK Block Diagram

Four control register bits, the external OSK pin, and the entire

32 bits of the ASF register govern the operation of the OSK

function. The primary control for the OSK block is the OSK

enable bit. When this bit is set, the OSK function is enabled;

otherwise, the OSK function is disabled. When disabled, the

other OSK input controls are ignored and the internal clocks are

shut down to conserve power.

When the OSK function is enabled, automatic and manual

operation is selected via the Select Auto-OSK bit. When this bit

is set, the automatic mode is active; otherwise, the manual

mode is active.

Manual OSK

In manual mode, output amplitude is varied by successive write

operations to the amplitude scale factor portion of the ASF register.

The rate at which amplitude changes can be applied to the output

signal is limited by the speed of the serial I/O port. In manual

mode, the OSK pin functionality depends on the state of the

manual OSK external control bit. It is either inoperative or used to

switch the output amplitude between the programmed amplitude

scale factor value and zero. When operational, a Logic 0 on the

OSK pin forces the output amplitude to zero whereas a Logic 1

on the OSK pin causes the output amplitude to be scaled by the

amplitude scale factor value.

Automatic OSK

In automatic mode, the OSK function automatically generates

a linear amplitude vs. time profile (or amplitude ramp). The

amplitude ramp is controlled via three parameters, as follows:

•

The maximum amplitude scale factor

•

The amplitude step size

•

The time interval between steps

The amplitude ramp parameters reside in the 32-bit ASF

amplitude step interval is set using the 16-bit amplitude ramp

rate portion of the ASF register (Bits[31:16]). The maximum

amplitude scale factor is set using the 14-bit amplitude scale

factor in the ASF register (Bits[15:2]). The amplitude step size

is set using the 2-bit amplitude step size portion of the ASF

negative slope) is controlled by the external OSK pin. When

the OSK pin is a Logic 1, the slope is positive; otherwise, it is

negative.

A 16-bit programmable timer that is clocked at a rate of ¼

fSYSCLK controls the step interval. The timer period sets the

interval between amplitude steps. The step time interval (Δt)

is given by

SYSCLK

∆

where M is the 16-bit number stored in the amplitude ramp rate

portion of the ASF register. For example, if fSYSCLK = 750 MHz

and M = 23,218 (0x5AB2), then Δt ≈ 123.8293 µs.

The output of the OSK function is a 14-bit unsigned data bus

that controls the amplitude of the DDS output (as long as the

OSK enable bit is Logic 1). When the OSK pin is Logic 1, the

OSK output value starts at 0 and increments by the programmed

amplitude step size until it reaches the programmed maximum

amplitude value. When the OSK pin is Logic 0, the OSK output

starts at its present value and decrements by the programmed

amplitude step size until it reaches 0.

The OSK output does not necessarily attain the maximum

amplitude—the OSK pin may switch to Logic 0 before attaining

the maximum value.

The OSK output does not necessarily reach a value of zero—the

OSK pin may switch to Logic 1 before attaining the zero value.

The OSK output is initialized to 0 at power-up. It is also set to 0

when the OSK enable bit is Logic 0 or when the OSK enable bit

is Logic 1, but the Select Auto-OSK bit is Logic 0.

The amplitude step size of the OSK output is set by the amplitude

step size bits in the ASF register according to the values listed in

Table 9. The step size refers to the LSB weight of the 14-bit OSK

output.

The OSK output cannot exceed the maximum amplitude value

programmed into the ASF register.

AD9957/PCBZ 数据表(PDF) 37 Page - Analog Devices

AD9957/PCBZ 数据表(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表下载