AD9957SLASHPCBZ datasheet(40/61 Pages) AD

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AD9957

Data Sheet

Rev. F | Page 40 of 61

SYNCHRONIZATION OF MULTIPLE DEVICES

OVERVIEW

The internal clocks of the AD9957 provide the timing for the

propagation of data along the baseband signal processing path.

These internal clocks are derived from the internal system clock

(SYSCLK) and are all submultiples of the SYSCLK frequency.

The logic state of all of these clocks in aggregate during any

given SYSCLK cycle defines a unique clock state. The clock state

advances with each cycle of SYSCLK, but the sequence of clock

states is periodic. By definition, multiple devices are synchro-

nized when their clock states match and they transition between

states simultaneously. Clock synchronization allows the user to

asynchronously program multiple devices, but synchronously

activate the programming by applying a coincident I/O update

to all devices. It also allows multiple devices to operate in unison

when the parallel port is in use with either the QDUC or inter-

polating DAC mode (see Figure 59) or when the dual serial port

(Blackfin interface) is in use.

The function of the synchronization logic in the AD9957 is to

force the internal clock generator to a predefined state coincident

with an external synchronization signal applied to the SYNC_IN

pins. Forcing multiple devices to the same clock state coincident

with the same external signal is, by definition, synchronization.

Figure 54 is a block diagram of the synchronization function.

The synchronization logic consists of two independent blocks, a

sync generator and a sync receiver, both of which use the local

SYSCLK signal for internal timing.

SYNC

GENERATOR

REF_CLK

SYSCLK

INTERNAL

CLOCKS

SYNC

RECEIVER

SYNC_OUT

REF_CLK

INPUT

CIRCUITRY

SYNC_IN

SYNC_SMP_ERR

SYNC

VALIDATION

DELAY

SYNC STATE

PRESET VALUE

SYNC

TIMING

VALIDATION

DISABLE

SETUP AND

HOLD VALIDATION

SYNC

RECEIVER

ENABLE

SYNC

RECEIVER

DELAY

INPUT DELAY

AND EDGE

DETECTION

Figure 54. Synchronization Circuit Block Diagram

The synchronization mechanism relies on the premise that the

REFCLK signal appearing at each device is edge aligned with all

others resulting from the external REFCLK distribution system

(see Figure 59).

CLOCK GENERATOR

The clock generator provides the necessary timing for the internal

workings of the AD9957. The goal of the synchronization

mechanism is to force the clock generator to a known state

coincident with an external synchronization signal. The clock

generator consists of three separate clock trees (see Figure 55).

The first is a common clock generator that is active for all

programmed modes of operation (single tone, QDUC, or

interpolating DAC). The common clock generates the

SYNC_CLK signal that appears at Pin 55. The second clock

generator is active when the device is programmed for the

interpolating DAC mode or quadrature modulation mode using

the parallel data port. It uses the SYSCLK/2 output of the common

clock as its primary timing source. The third clock generator is

active when the device is programmed for quadrature modulation

mode using the Blackfin interface.

SYSCLK

PDCLK

COMMON CLOCK

GENERATOR

SYNC_CLK

CLOCK GENERATOR FOR

QUADRATURE MODULATION MODE

WITH THE BLACKFIN INTERFACE

SYNC

PULSE

SYNC STATE

PRESET VALUE

CLOCK GENERATOR FOR INTERPOLATING

DAC MODE OR QUADRATURE MODULATION

MODE WITH THE PARALLEL DATA PORT

÷2

÷R

Figure 55. Clock Generator

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