AD9957SLASHPCBZ datasheet(6/61 Pages) AD

6 / 61 page

AD9957

Data Sheet

Rev. F | Page 6 of 61

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

NOISE SPECTRAL DENSITY (NSD)

Single Tone

fOUT = 20.1 MHz

−167

dBm/Hz

fOUT = 98.6 MHz

−162

dBm/Hz

fOUT = 201.1 MHz

−157

dBm/Hz

fOUT = 397.8 MHz

−151

dBm/Hz

TWO-TONE INTERMODULATION DISTORTION (IMD)

I/Q rate = 62.5 MSPS;

16× interpolation

fOUT = 25 MHz

−82

dBc

fOUT = 50 MHz

−78

dBc

fOUT = 100 MHz

−73

dBc

MODULATOR CHARACTERISTICS

Input Data

Error Vector Magnitude

2.5 Msymbols/s, QPSK,

4× oversampled

0.53

270.8333 ksymbols/s, GMSK,

32× oversampled

0.77

2.5 Msymbols/s, 256-QAM,

4× oversampled

0.35

WCDMA—FDD (TM1), 3.84 MHz Bandwidth,

5 MHz Channel Spacing

Adjacent Channel Leakage Ratio (ACLR)

IF = 143.88 MHz

−78

dBc

Carrier Feedthrough

−78

dBc

SERIAL PORT TIMING CHARACTERISTICS

Maximum SCLK Frequency

Mbps

Minimum SCLK Pulse Width

Low

High

Maximum SCLK Rise/Fall Time

Minimum Data Setup Time to SCLK

Minimum Data Hold Time to SCLK

Maximum Data Valid Time in Read Mode

I/O_UPDATE/PROFILE2 to PROFILE 0/RT TIMING CHARACTERISTICS

Minimum Pulse Width

High

SYNC_CLK cycle

Minimum Setup Time to SYNC_CLK

1.75

Minimum Hold Time to SYNC_CLK

I/Q INPUT TIMING CHARACTERISTICS

Maximum PDCLK Frequency

250

MHz

Minimum I/Q Data Setup Time to PDCLK

1.75

Minimum I/Q Data Hold Time to PDCLK

Minimum TxENABLE Setup Time to PDCLK

1.75

Minimum TxENABLE Hold Time to PDCLK

MISCELLANEOUS TIMING CHARACTERISTICS

Wake-Up Time3

Fast Recovery Mode

SYSCLK cycles4

Full Sleep Mode

150

μs

Minimum Reset Pulse Width High

SYSCLK cycles4

DATA LATENCY (PIPELINE DELAY)

Data Latency Single Tone Mode

Frequency, Phase-to-DAC Output

SYSCLK cycles4

AD9957/PCBZ 数据表(PDF) 6 Page - Analog Devices

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AD9957/PCBZ 数据表(PDF) 6 Page - Analog Devices

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