AD9957SLASHPCBZ datasheet(4/61 Pages) AD

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AD9957

Data Sheet

Rev. F | Page 4 of 61

REVISION HISTORY

4/2018—Rev. E to Rev. F

Moved Sync Generator Section .................................................... 41

Changes to Sync Generator Section, Figure 56, and Sync

Receiver Section.............................................................................. 41

5/2017—Rev. D to Rev. E

Changes to External PLL Loop Filter Components Section..... 36

1/2016—Rev. C to Rev. D

Changes to Table 3.......................................................................... 11

Changes to Figure 27...................................................................... 18

4/2012—Rev. B to Rev. C

Changes to Table 1............................................................................ 7

Changes to Table 3.......................................................................... 11

Change to Sync Generator Section............................................... 41

Changes to Sync Receiver Section and Setup/Hold Validation

Section.............................................................................................. 42

Changes to Table 13........................................................................ 50

Changes to Table 19........................................................................ 57

Changes to Table 26........................................................................ 59

10/2010—Rev. A to Rev. B

Changes to Data Rate in Features Section..................................... 1

Changes to Specifications Section .................................................. 6

Added EPAD Notation to Figure 4 and Table 3 ........................... 9

Changes to XTAL_SEL Pin Description...................................... 11

Changes to BlackFin Interface (BFI) Mode Section .................. 18

Changes to Figure 30 and Figure 31............................................. 22

Changes to Programmable Interpolating Filter Section............ 24

Changes to Fifth Paragraph of Quadrature Modulator Section......25

Changes to RAM Segment Registers Section ............................. 27

Changes to RAM Playback Operation Section........................... 28

Changes to Control Interface—Serial I/O Section..................... 47

Added to I/O_UPDATE, SYNC_CLK, and System Clock

Relationships Section and Figure 64 ............................................ 49

Changes to Default Values of Profile 0 Register—Single Tone

(0x0E) and Profile 0 Register—QDUC (0x0E) in Table 14....... 51

Changes to Default Values in Table 15......................................... 52

Changes to Default Values in Table 16......................................... 53

Changes to Default Values in Table 17......................................... 54

Updated Outline Dimensions ....................................................... 61

1/2008—Rev. 0 to Rev. A

Changes to REFCLK Multiplier Specification...............................3

Changes to I/O_UPDATE/Profile<2:0>/RT Timing

Characteristics and I/Q Input Timing Characteristics.................5

Replaced Pin Configuration and Function Descriptions

Section.................................................................................................8

Changes to Figure 25 Through Figure 29.................................... 15

Deleted Table 4, Renumbered Sequentially ................................ 20

Changes to DDS Core Section...................................................... 24

Changes to Figure 47 and Table 6................................................. 33

Replaced Synchronization of Multiple Devices Section............ 39

Added I/Q Path Latency Section.................................................. 44

Added Power Supply Partitioning Section.................................. 45

Changes to General Serial I/O Operation Section..................... 46

Changes to Table 13 ....................................................................... 48

Changes to Table 14 ....................................................................... 49

Changes to Table 19 ....................................................................... 54

Changes to Table 20 ....................................................................... 56

Changes to GPIO Configuration Register and

GPIO Data Register Sections ........................................................ 58

5/2007—Revision 0: Initial Version

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