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AD9957/PCBZ 数据表(PDF) 5 Page - Analog Devices |
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AD9957/PCBZ 数据表(HTML) 5 Page - Analog Devices |
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5 / 61 page  Data Sheet AD9957 Rev. F | Page 5 of 61 SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) = 3.3 V ± 5%, DVDD_I/O (3.3V) = 3.3 V ± 5%, T = 25°C, RSET = 10 kΩ, IOUT = 20 mA, external reference clock frequency = 1000 MHz with REFCLK multiplier disabled, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit REF_CLK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled 60 10001 MHz Enabled 3.2 60 MHz Maximum REFCLK Input Divider Frequency Full temperature range 1500 1900 MHz Minimum REFCLK Input Divider Frequency Full temperature range 25 35 MHz External Crystal 25 MHz Input Capacitance 3 pF Input Impedance (Differential) 2.8 kΩ Input Impedance (Single-Ended) 1.4 kΩ Duty Cycle REFCLK multiplier disabled 45 55 % REFCLK multiplier enabled 40 60 % REF_CLK Input Level Single-ended 50 1000 mV p-p Differential 100 2000 mV p-p REFCLK MULTIPLIER VCO GAIN CHARACTERISTICS VCO Gain (KV) at Center Frequency VCO0 range setting 429 MHz/V VCO1 range setting 500 MHz/V VCO2 range setting 555 MHz/V VCO3 range setting 750 MHz/V VCO4 range setting 789 MHz/V VCO5 range setting2 850 MHz/V REFCLK_OUT CHARACTERISTICS Maximum Capacitive Load 20 pF Maximum Frequency 25 MHz DAC OUTPUT CHARACTERISTICS Full-Scale Output Current 8.6 20 31.6 mA Gain Error −10 +10 %FS Output Offset 2.3 µA Differential Nonlinearity 0.8 LSB Integral Nonlinearity 1.5 LSB Output Capacitance 5 pF Residual Phase Noise At 1 kHz offset, 20 MHz AOUT REFCLK Multiplier Disabled −152 dBc/Hz Enabled at 20× −140 dBc/Hz Enabled at 100× −140 dBc/Hz AC Voltage Compliance Range −0.5 +0.5 V SPURIOUS-FREE DYNAMIC RANGE (SFDR SINGLE TONE) fOUT = 20.1 MHz −70 dBc fOUT = 98.6 MHz −69 dBc fOUT = 201.1 MHz −61 dBc fOUT = 397.8 MHz −54 dBc |
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