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AD9957

Data Sheet

Rev. F | Page 44 of 61

SYNCHRONIZATION EXAMPLE

To accomplish the synchronization of multiple devices provide

each AD9957 with a SYNC_IN signal that is edge aligned across

all the devices. If the SYNC_IN signal is edge aligned at all devices,

and all devices have the same sync receiver delay and sync state

preset value, then they all have matching clock states (that is,

they are synchronized). Figure 59 shows this concept with three

AD9957s in synchronization. One device operates as a master

timing unit with the others synchronized to the master.

The master device must have its SYNC_IN pins included as part

of the synchronization distribution and delay equalization mecha-

nism. This ensures that the master maintains synchronous timing

with the other units.

The synchronization mechanism begins with the clock distribu-

tion and delay equalization block, which ensures that all devices

receive an edge-aligned REFCLK signal. However, even though

the REFCLK signal is edge aligned among all devices, this alone

does not guarantee that the clock state of each internal clock

generator is coordinated with the others. This is the role of the

synchronization and delay equalization block. This block accepts

the SYNC_OUT signal generated by the master device and

redistributes it to the SYNC_IN input of the slave units (as well

as feeding it back to the master). The goal of the redistributed

SYNC_OUT signal from the master device is to deliver an edge-

aligned SYNC_IN signal to all of the sync receivers.

Assuming that all devices share the same REFCLK edge timing

(due to the clock distribution and delay equalization block) and

that all devices share the same SYNC_IN edge timing (due to

the synchronization and delay equalization block), then all

devices should be generating an internal sync pulse in unison

(assuming all have the same value for the sync receiver delay).

With the further stipulation that all devices have the same sync

state preset value, then the synchronized sync pulses cause all of

the devices to assume the same predefined clock state simultane-

ously. That is, all devices have their internal clocks fully

synchronized.

CLOCK

SOURCE

SYNC

OUT

REF_CLK

AD9957

NUMBER 1

MASTER DEVICE

FPGA

DATA

FPGA

DATA

FPGA

DATA

EDGE

ALIGNED

AT REF_CLK

INPUTS

EDGE

ALIGNED

AT SYNC_IN

INPUTS.

SYNC

OUT

REF_CLK

AD9957

NUMBER 2

SYNC

OUT

REF_CLK

AD9957

NUMBER 3

(FOR EXAMPLE, AD951x)

CLOCK DISTRIBUTION

AND

DELAY EQUALIZATION

SYNCHRONIZATION

DISTRIBUTION AND

DELAY EQUALIZATION

(FOR EXAMPLE AD951x)

Figure 59. Multichip Synchronization Example

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