AD9957SLASHPCBZ datasheet(41/61 Pages) AD

41 / 61 page

Data Sheet

AD9957

Rev. F | Page 41 of 61

SYNC GENERATOR

The sync generator block is shown in Figure 56. It is activated

via the Sync Generator Enable bit. It allows for one AD9957 in a

group to function as a master timing source with the remaining

devices slaved to the master.

SYSCLK

SYNC

GENERATOR

ENABLE

SYNC

GENERATOR

DELAY

SYNC

POLARITY

SYNC_OUT

D Q

PROGAMMABLE

DELAY

÷16

÷R

LVDS

DRIVER

Figure 56. Sync Generator

The sync generator produces an LVDS-compatible clock signal

with a 50% duty cycle that appears at the SYNC_OUT pins. The

frequency of the SYNC_OUT signal can be one of two possible

rates. With the AD9957 programmed for any of the following

modes:

•

Single tone mode

•

Quadrature modulation mode with the CCI filter bypassed

(that is, interpolation factor is 1)

•

Interpolating DAC mode with the CCI filter bypassed (that

is, interpolation factor is 1)

The frequency of SYNC_OUT is given by:

SYSCLK

OUT

SYNC

With the AD9957 programmed for the QDUC or interpolating

DAC mode and with the CCI filter not bypassed (that is, R > 1)

the frequency of SYNC_OUT is given by

SYSCLK

SYNC OUT

where R is the programmed interpolation factor of the CCI filter.

The signal at the SYNC_OUT pins is edge aligned with either

the rising or falling edge of the internal SYSCLK signal as deter-

mined by the Sync Polarity bit. Because the SYNC_OUT signal is

synchronized with the internal SYSCLK of the master device, the

master device SYSCLK serves as the reference timing source for

all slave devices.

The user can adjust the output delay of the SYNC_OUT signal

in steps of ~75 ps by programming the 5-bit sync generator

delay word via the serial I/O port. The programmable output

delay facilitates added edge timing flexibility to the overall

synchronization mechanism.

SYNC RECEIVER

The sync receiver block (shown in Figure 57) is activated via

the Sync Receiver Enable bit. The sync receiver consists of

three subsections: the input delay and edge detection block,

the internal clock generator block, and the setup-and-hold

validation block.

The clock generator block remains operational even when the

sync receiver is not enabled.

The sync receiver accepts an LVDS-compatible signal and

includes an internal 100 Ω termination across the SYNC_IN

pins. Typically, the signal applied to the SYNC_IN pins originates

from the SYNC_OUT of another AD9957 functioning as a

master timing unit. The sync receiver expects a periodic

synchronization pulse that meets certain frequency requirements

based on the operating mode of the AD9957. When programmed

for single tone mode, the frequency of SYNC_IN must satisfy

SYSCLK

SYNC

where M is any integer greater than zero. When programmed

for quadrature modulation mode (using the parallel data port)

or interpolating DAC mode, the frequency of SYNC_IN must

satisfy

(

)

SYSCLK

SYNC

where R is the programmed CCI interpolation factor and M is

any integer greater than or equal to zero. When programmed

for quadrature modulation mode using the Blackfin interface,

the frequency of SYNC_IN must satisfy

(

)

SYSCLK

SYNC

where R is the programmed CCI interpolation factor and M is

any integer greater than or equal to zero.

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