RA4M1 datasheet(3/130 Pages) RENESAS

3 / 130 page

R01DS0355EJ0100 Rev.1.00

Page 3 of 130

Oct 8, 2019

RA4M1 Group

1. Overview

Overview

The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set

of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU provides an optimal combination of low-power, high-performance Arm Cortex®-M4 core running up to

48 MHz with the following features:

 256-KB code flash memory

 32-KB SRAM

 Segment LCD Controller (SLCDC)

 Capacitive Touch Sensing Unit (CTSU)

 USB 2.0 Full-Speed Module (USBFS)

 14-bit A/D Converter (ADC14)

 12-bit D/A Converter (DAC12)

 Security features.

1.1

Function Outline

Table 1.1

Arm core

Feature

Functional description

Arm Cortex-M4 core

 Maximum operating frequency: up to 48 MHz

 Arm Cortex-M4 core

- Revision: r0p1-01rel0

- Armv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.

 Arm Memory Protection Unit (Arm MPU)

- Armv7 Protected Memory System Architecture

- 8 protected regions.

 SysTick timer

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2

Memory

Feature

Functional description

Code flash memory

Maximum 256-KB code flash memory. See section 44, Flash Memory in User’s Manual.

Data flash memory

8-KB data flash memory. See section 44, Flash Memory in User’s Manual.

Option-setting memory

The option-setting memory determines the state of the MCU after a reset. See section 6,

Option-Setting Memory in User’s Manual.

SRAM

On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). An area in

SRAM0 provides error correction capability using ECC. See section 43, SRAM in User’s

Manual.

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