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RA4M1 数据表(PDF) 73 Page - Renesas Technology Corp

部件名 RA4M1
功能描述  High efficiency 48-MHz Arm Cortex-M4 core, 256-KB code flash memory
PDF  130 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RA4M1 数据表(HTML) 73 Page - Renesas Technology Corp

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R01DS0355EJ0100 Rev.1.00
Page 73 of 130
Oct 8, 2019
RA4M1 Group
2. Electrical Characteristics
Figure 2.50
SCI simple SPI mode timing for slave when CKPH = 0
Note 1.
tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Note 2.
Cb indicates the total capacity of the bus line.
Table 2.35
SCI timing (3)
Conditions: VCC = 2.7 to 5.5 V
Parameter
Symbol
Min
Max
Unit
Test conditions
Simple I2C
(Standard mode)
SDA input rise time
tSr
-
1000
ns
Figure 2.51
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc*1
ns
Data input setup time
tSDAS
250
-
ns
Data input hold time
tSDAH
0-
ns
SCL, SDA capacitive load
Cb*2
-
400
pF
Simple I2C
(Fast mode)
SDA input rise time
tSr
-
300
ns
Figure 2.51
For all ports
except P408, use
PmnPFS.DSCR
of middle drive.
For port P408,
use
PmnPFS.DSCR1
/DSCR of middle
drive for IIC
fast-mode.
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc*1
ns
Data input setup time
tSDAS
100
-
ns
Data input hold time
tSDAH
0-
ns
SCL, SDA capacitive load
Cb*1
-
400
pF
tDr, tDf
tSA
tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data)
DATA
MSB OUT
MSB IN
DATA
LSB IN
MSB IN
LSB OUT
tSU
tOD
tREL
MSB OUT
SSn
input
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
MISOn
output
MOSIn
input
(n = 0 to 2, 9)



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