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RA4M1 数据表(PDF) 69 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 69 Page - Renesas Technology Corp |
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69 / 130 page  R01DS0355EJ0100 Rev.1.00 Page 69 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics Note 1. tPBcyc: PCLKB cycle. Note 2. tcac: CAC count clock source cycle. 2.3.8 SCI Timing Note 1. tPcyc: PCLKA cycle. Figure 2.44 SCK clock input timing Table 2.33 SCI timing (1) Parameter Symbol Min Max Unit*1 Test conditions SCI Input clock cycle Asynchronous tScyc 4- tPcyc Figure 2.44 Clock synchronous 6 - Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr -20 ns Input clock fall time tSCKf -20 ns Output clock cycle Asynchronous tScyc 6- tPcyc Clock synchronous 4 - Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time 1.8 V or above tSCKr -20 ns 1.6 V or above - 30 Output clock fall time 1.8 V or above tSCKf -20 ns 1.6 V or above - 30 Transmit data delay (master) Clock synchronous 1.8 V or above tTXD -40 ns Figure 2.45 1.6 V or above - 45 Transmit data delay (slave) Clock synchronous 2.7 V or above - 55 ns 2.4 V or above - 60 1.8 V or above - 100 1.6 V or above - 125 Receive data setup time (master) Clock synchronous 2.7 V or above tRXS 45 - ns 2.4 V or above 55 - 1.8 V or above 90 - 1.6 V or above 110 - Receive data setup time (slave) Clock synchronous 2.7 V or above 40 - ns 1.6 V or above 45 - Receive data hold time (master) Clock synchronous tRXH 5- ns Receive data hold time (slave) Clock synchronous tRXH 40 - ns tSCKW tSCKr tSCKf tScyc SCKn (n = 0 to 2, 9) |
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